Abstract: A semiconductor integrated circuit includes an input circuit for taking in signals and an output circuit for outputting signals. The input circuit is so set that the input impedance during input signal transition is lower than the input impedance on other occasions than input signal transition. The output circuit is so set that the driving force during the second half of signal transition is lower than the driving force during the first half of transition. Such setting that the input impedance during input signal transition is lower than the input impedance on other occasions than input signal transition reduces reflected waves during input signal transition. Such setting that the driving force during the second half of signal transition is lower than the driving force during the first half of transition suppresses production of reflected waves during the second half of signal transition.

Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

Abstract: In order to realize individually and easily optimization of exposure conditions such as exposure dose and focus by photolithography in a production process of semiconductor devices, the present invention is such that: light is radiated onto a pattern on a semiconductor wafer; by an optical system that detects information on a pattern shape using scattered light by its reflection, waveforms of an FEM sample wafer having a plurality of shape deformation patterns prepared in advance are detected and stored; one or more characteristic points on a spectral waveform generated in association with a pattern change is recorded; and a variation model of the characteristic points is obtained. As to a pattern to be measured, a spectral waveform is detected in the same manner as that described above, and deviations (exposure dose deviation and focus deviation) of the formation conditions are estimated from a displacement of the characteristic points on the waveform using the variation model.

Abstract: In a semiconductor module connecting a semiconductor element and a passive element to a printed board, each of connection portions between the semiconductor element and the printed board and between the passive element and the printed board includes a metal with a melting point of 260° C. or higher and an intermetallic compound with a melting point of 260° C. or higher. Specifically, by connecting them using Pb-free solder with a melting point of 260° C. or lower, the printed board capable of lowering in cost, lightening, and reducing back height can be applied to a module board.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: A clock generation circuit receives a reference clock signal for outputting clock signals to peripheral circuits. A duty ratio of at least one of output buffer signals output from buffer circuits included in the clock generation circuit is varied so that a duty ratio of at least one of the clock signals can be varied.

Abstract: An RF power module in which operating voltage is controlled by a control signal based on amplitude information includes a temperature detecting device which is provided over a semiconductor chip formed with an amplifying transistor or a semiconductor chip formed with a power source circuit; and a detector having a hysteresis characteristic which is provided over the semiconductor chip formed with the device or a different semiconductor chip, applies a bias to the temperature detecting device to compare the state of the device at two reference levels, outputs a signal indicating abnormality when judging that the temperature of the semiconductor chip formed with the temperature detecting device is above a predetermined temperature, and outputs a signal indicating normality when judging that the temperature of the semiconductor chip is below a second predetermined temperature lower than the predetermined temperature.

Abstract: A probe card is formed of a main board and a sub-board located above the principal surface of the main board. The sub-board is located inside of an internal circumferential pad region of the main board. Relays are arranged in a line along the external circumference of the upper surface of the sub-board. Electrical components, such as the relays, a capacitor, a crystal-controlled oscillator, and an IC, are selected from components which are reduced in size as much as possible. The circuit for inspection is formed of the electrical components provided over the sub-board and the wiring layers within the sub-board. As a result, the yield of the probe card can be improved.

Abstract: For writing K-bit write data in parallel (K is integer at least 2), bit lines each arranged for each memory cell columns and at least K current return lines are provided. K selected bit lines to write the K-bit write data are connected in series in a single current path. When data having different levels are written through adjacent selected bit lines, the selected bit lines are connected to each other at their one ends or the other ends, so that a bit line write current flowing through the former selected bit line is directly transmitted to the latter selected bit line. On the other hand, when data having the same level are written through adjacent selected bit lines, a bit line write current flowing through the former selected bit line is turned back by the corresponding current return line, and then transmitted to the latter selected bit line.

Abstract: Electrical testing is to be performed on a semiconductor integrated circuit device which the test pads formed. To facilitate such testing, the method of manufacture of the semiconductor integrated circuit device employs a probe card which has two or more contact terminals which can contact two or more electrodes. This probe card includes, in opposition to a wiring substrate of the semiconductor integrated circuit device in which a first wiring is formed, a first sheet having two or more contact terminals to contact the two or more electrodes; a second wiring electrically connected to the two or more contact terminals and the first wiring; and first dummy wirings which are near the region of formation of the two or more contact terminals, are arranged to a non-forming region of the second wiring, and do not participate in signal transfer.

Abstract: After a digit line is charged to a power supply voltage by turn-on of a first switching element, the first switching element is turned off and a second switching element is turned on, whereby the digit line is connected to a ground voltage. Similarly, in order to feed data write current, a bit line is charged to a data voltage in accordance with write data through a third switching element. Then, the bit line is connected to a voltage different from the data voltage by a fourth switching element while the third switching element is turned off. Therefore, a load current from a power supply to an MRAM device is supplied during charging of a digit line capacitance and a bit line capacitance, without being consumed when the data write current flows. Consequently, a peak of the load current supplied from the power supply is suppressed.

Abstract: A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor are electrically connected with each other through the SOI layer located under the element isolation insulating film. Therefore, the access transistor is in a DTMOS structure having the gate electrode connected with the body region through the contact, which in turn is also electrically connected to the body region of the driver transistor. Thus, operations can be stabilized while suppressing increase of an area for forming the SRAM cell.

Abstract: Magnetic memory devices integrated together with a logic circuit on a common semiconductor chip are arranged to have layouts mirror-symmetrical (mirror inversion) with respect to an axis parallel to a magnetization-hard axis of a magneto-resistance element of a magnetic memory cell in the magnetic memory device. The logic circuit is arranged between the magnetic memory devices. The magnetic memory device capable accurately of maintaining integrity in logical level between write data and read data is achieved.

Abstract: Productivity is to be improved in assembling a semiconductor integrated circuit device. A matrix substrate is provided and semiconductor chips are disposed on a first heating stage, and then the matrix substrate is disposed above the semiconductor chips on the first heating stage. Subsequently, the semiconductor chips and the matrix substrate are bonded to each other temporarily by thermocompression bonding, while heating the chips directly by the first heating stage. Thereafter, the temporarily bonded matrix substrate is disposed on a second heating stage adjacent to the first heating stage, and then, on the second heating stage, the semiconductor chips are thermocompression-bonded to the matrix substrate, while being heated directly by the second heating stage.

Abstract: A power MISFET, which has a desired gate breakdown voltage, can be manufactured will controlling an increase in parasitic capacitance. After depositing a polycrystalline silicon film on a substrate and embedding groove portions in the polycrystalline silicon film by patterning the polycrystalline silicon film in an active cell area, a gate electrode is formed within the groove portion, and the inside of the groove portion is embedded in a gate wiring area. Extending to the outside of the groove portion continuously out of the groove portion, there is a gate drawing electrode electrically connected to the gate electrode. Slits extending from the end portion of the gate drawing electrode are formed in the gate drawing electrode outside of the groove portion. Then, a silicon oxide film and a BPSG film are deposited on the substrate.

Abstract: On an adapter mounting portion 3a having a projecting cross section which is formed on a cap 3 of a small-sized memory card 1, a recessed portion of an adapter 2 side is fitted so that both parts are formed as an integral unit in a replaceable manner. Accordingly, the small-sized memory card 1 can maintain the dimensional compatibility with respect to existing memory cards whereby the small-sized memory card 1 can be used also in equipment which is designed to cope with the existing memory cards.

Abstract: In a high frequency power amplifier circuit in which bias voltages are applied to the transistors for amplification by current mirroring, this invention enables preventing waveform distortion near the peak output power level by allowing sufficient idle currents to flow through the transistors for amplification, while enhancing the power efficiency in a low output power region. The power amplifier includes a detection circuit comprising a transistor for detection which receives the AC component of an input signal to the last-stage transistor for amplification at its control terminal, a current mirror circuit which mirrors current flowing through that transistor, and a current-voltage conversion means which converts current flowing in the slave side of the current mirror circuit into a voltage.

Abstract: A search payload data shift part has n latch parts LT1 to LTn (n?2), each of which can store 1-byte latch data, and obtains search payload data having an n-byte length, while shifting payload data inputted from an input terminal, in synchronization with a clock provided from the exterior. Data related to the search payload data is given to a CAM array, as search object data. When the search object data matches entry data of the CAM array, a hit signal ‘hit’ indicating a match is outputted from the CAM array.

Abstract: A voltage supply control circuit is arranged between a true ground voltage and a pseudo ground line. In an active mode, first and second control signals are at the “H” and “L” levels, respectively. In response to this, a first switch is turned on so that a first node is electrically coupled to a power supply voltage, and attains the “H” level. Further, a second switch is turned on to couple electrically the ground voltage to a second node. In a standby mode, the first and second control signals are at the “L” and “H” levels, respectively. In response to this, a third switch is turned on to couple electrically the first and second nodes together. Since the power supply voltage was electrically coupled to the first node according to the turn-on of the first switch in the active mode, the path of the control signal including the first node to the switch has accumulated charged charges.