Abstract: On a semiconductor substrate a silicon oxide film is formed and provided with a recess. In the recess a reflector layer of copper is disposed as a blocking layer with a barrier metal posed therebetween. The reflector layer of copper is covered with a silicon oxide film and thereon a fuse region provided with a plurality of fuses is provided. The reflector layer of copper has a plane of reflection recessed downward to reflect a laser beam. The reflector layer of copper is arranged to overlap substantially the entirety of the fuse region, as seen in a plane. A laser beam radiated to blow the fuse can have a reduced effect on a vicinity of the fuse region. A semiconductor device reduced in size can be obtained.

Abstract: The invention provides a semiconductor device capable of protecting a low-concentration implantation region from contamination, and a method for manufacturing the same. A photoresist is formed on a TEOS film which is formed all over a substrate, and removed by photo engraving so as to be partially left. This photo resist is of a positive or negative type opposite to a type of a photoresist used for formation of a p-offset region and a diffusion region. Then, the TEOS film is etched back except for a portion just under the photoresist. Thereby, a contamination protective film is formed just under the photoresist, and a side wall is formed on a side face of a gate electrode.

Abstract: An insulating film provided below a floating gate electrode includes a first insulating film located at both end portions below the floating gate electrode, and a second insulating film sandwiched between the first insulating films and located in a middle portion below the floating gate electrode. The first insulating film and the second insulating film are formed in separate steps, and the first insulating film is thicker than the second insulating film. With this structure, when an insulating film is provided between the floating gate electrode and a silicon substrate to have a thickness more increased at its end portion than at its middle portion, the thickness can be increased more freely and a degree of the increase can be controlled more readily.

Abstract: To provide a semiconductor device having a structure in which a barrier metal film containing nitrogen is formed in a connection surface between a copper alloy wiring and a via, in which the electric resistance between the copper alloy wiring and the via can be prevented from rising, and the electric resistance can be prevented from varying. A semiconductor device according to the present invention comprises a first copper alloy wiring, a via and a first barrier metal film. The first copper alloy wiring is formed in an interlayer insulation film and contains a predetermined additive element in a main component Cu. The via is formed in an interlayer insulation film and electrically connected to the upper surface of the first copper alloy wiring. The first barrier metal film is formed so as to be in contact with the first copper alloy wiring in the connection part between the first copper alloy wiring and the via and contains nitrogen.

Abstract: A semiconductor memory device has the group of longest signal lines configured in a twisted wiring scheme, the group of signal lines of intermediate length configured in a shield wiring scheme, and the group of shortest signal lines configured in a single wiring scheme. As a whole, degradation in signal waveform and improvement in layout efficiency can both be achieved.

Abstract: In a driver circuit constructing a switching power supply device that switches power transistors passing a current through a coil by a PWM mode, a current detection transistor, which is smaller in size than the low-potential side power transistor and a current detection resistor are provided in parallel to the low-potential side power transistor. The same control voltage as the power transistor is applied to the control terminal of the current detection transistor. An operational amplifier is formed, that has the potential of the connection node between the current detection transistor and the current detection resistor applied to its inverse input terminal and a feedback loop, so as to make a pair of input terminals of the operational amplifier be at the same potential. A signal produced by the current detection resistor is thus outputted as a current detection signal.

Abstract: The present invention provides a semiconductor integrated circuit device having an SRAM in which leak current is reduced. In an SRAM comprising a plurality of memory cells each constructed by a storage in which input and output terminals of two inverter circuits are cross-connected and a selection MOSFET provided between the storage and complementary bit lines and whose gate is connected to a word line, a substrate bias switching circuit is provided. In normal operation, the substrate bias switching circuit supplies a power source voltage to an N-type well in which a P-channel MOSFET of a memory cell is formed and supplies a ground potential of the circuit to a P-type well in which an N-channel MOSFET is formed.

Abstract: Memory cells are disposed in plural array form. Select gate electrodes of the memory cells arranged in an X direction are connected to one another by select gate lines respectively. Memory gate electrodes are connected by memory gate lines respectively. The memory gate lines respectively connected to the memory gate electrodes of the memory cells adjacent to one another through source regions interposed therebetween are not electrically connected to one another. Each of the select gate lines has a first portion that extends in the X direction, and a second portion 9b of which one end is connected to the first portion and extends in a Y direction. The memory gate line is formed on its corresponding sidewall of the select gate line with an insulating film interposed therebetween.

Abstract: In an A/D converter and a microcontroller including the same, the number of selection patterns of analog input channels is increased for each A/D conversion and the A/D conversion is conducted using an A/D converter having only fundamental functions without imposing load onto a CPU. The A/D converter or a DMA transfer device includes an A/D conversion table including one or more entries. Each entry includes enable bits for setting whether or not an A/D conversion is executed for the respective analog input channels and a plurality of count number bits for setting a number of executions of the A/D conversion.

Abstract: In a semiconductor integrated circuit device in which a rectifier device constituting a rectifier comprises a MOS transistor whose gate is connected to one antenna terminal and whose source is connected to the other antenna terminal, the parasitic capacitance applied between the antenna terminals increased. The present invention provides a technology for connecting a first MOS transistor whose gate is connected to a second input terminal between a first input terminal and a first output terminal, allowing an output terminal of a first bulk terminal control circuit, which is connected between the first and second input terminals, to control a bulk terminal of the first MOS transistor, and allowing an output terminal of a second bulk terminal control circuit, which is connected between the first and second input terminals, to control a bulk terminal of a second MOS transistor, which is connected between the second input terminal and the first output terminal.

Abstract: A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film (20) and a silicon nitride film (21) being formed, p-type impurity ions (231, 232) are implanted in a Y direction from diagonally above. As for an implant angle ? of the ion implantation, an implant angle is adopted that satisfies the relationship tan?1(W2/T)<??tan?1(W1/T), where W1 is an interval between a first portion (211) and a fourth portion (214) and an interval between a third portion (213) and a sixth portion (216); W2 is an interval between a second portion (212) and a fifth portion (215); T is a total film thickness of the silicon oxide film (20) and the silicon nitride film (21). When the implant angle ? is controlled within that range, impurity ions (231, 232) are implanted into a second side surface (10A2) and a fifth side surface (10A5) through a silicon oxide film (13).

Abstract: A high frequency power amplifier electronic component (RF power module) is so constituted as to apply bias to an amplifier FET in current mirror configuration. In this RF power module, deviation of a bias point due to the short channel effect of the FET is corrected, and variation in high frequency power amplifier characteristics reduced. The high frequency power amplifier circuit (RF power module) is so constituted that the bias voltage for the amplifier transistor in a high frequency power amplifier circuit is supplied from a bias transistor connected with the amplifier transistor in current mirror configuration. In addition to a pad (external terminal) connected with the control terminal of the amplifier transistor, a second pad is provided which is connected with the control terminal of the bias transistor connected with the amplifier transistor in current mirror configuration.

Abstract: To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit) information to be written are synthesized by a write data conversion circuit for each of the write operations carried out three times. In this way, the four-value (two-bit) information are written into one memory cell, and the memory capacity of the memory cell can be increased. In the information read operation, three different kinds of voltages are applied to a word line, three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit and the memory information of the memory cell are converted to the two-bit information.

Abstract: A plurality of conductive layers and a plurality of wiring layers connecting a supporting substrate having SOI structure and uppermost wire are formed along a peripheral part of a semiconductor chip together with the uppermost wire, to thereby surround a transistor forming region in which a transistor is to be formed.

Abstract: One of the aspects of the present invention is to provide a semiconductor device, which includes a circuit board, a first semiconductor chip mounted on the circuit board, a built-in semiconductor package on the first semiconductor chip, and a first molded resin encompassing the first semiconductor chip and the built-in semiconductor package. The built-in semiconductor package includes at least one second semiconductor chip mounted on a die pad, and the second semiconductor chip has a plurality of terminals. Also, the built-in semiconductor package includes a plurality of lead frames, and each of the lead frames is electrically connected with respective one of the terminals of the second semiconductor chip, and has a connection region on one side and a support region on the other opposing side.

Abstract: A method of manufacturing a semiconductor device according to the present invention includes the steps of introducing first impurities of a first conductivity type into a main surface of a semiconductor substrate 1 to form a first impurity region, introducing second impurities of a second conductivity type to form a second impurity region, forming a first nickel silicide film on the first impurity region and forming a second nickel silicide film on the second impurity region, removing an oxide film formed on each of the first and second nickel silicide films by using a mixed gas having an NH3 gas and a gas containing a hydrogen element mixed therein, and forming a first conducting film on the first nickel silicide film and forming a second conducting film on the second nickel silicide film, with the oxide film removed.

Abstract: In performing address translation from a virtual address space to a physical address space, when the virtual address space is divided into an area (P0), which is subjected to the address translation by TLB, and areas (P1 and P2), which are fixedly mapped to the physical address without being subjected the address translation, future extension of the physical address become difficult. A data processor comprises an address translation unit ATU that receives virtual address output from the CPU and outputs a physical address; the ATU includes a first translation lookaside buffer UTLB, a second translation lookaside buffer DTLB, a control circuit TLB_CTL that selects one of a first and a second translation lookaside buffers and performs address translation in accordance with an area of an address space in the virtual address.

Abstract: There is provided a semiconductor device having a wiring structure which reduces possibility of a short circuit, and method of making the device. Besides, there is provided a semiconductor device having high reliability. Further, there is provided a semiconductor device having high yield. A wiring line is formed at one main surface side of a semiconductor substrate, and has a laminate structure of an adjacent conductor layer and a main wiring layer. The main wiring layer contains an added element to prevent migration. The adjacent conductor layer is formed of a material for preventing a main constituent element and the added element of the main wiring layer from diffusing into the substrate beneath the adjacent conductor layer, and the concentration of the added element at a location close to an interface between the adjacent conductor layer and the main wiring layer is low compared to the concentration of the added element in the main wiring layer spaced from the adjacent conductor layer.

Abstract: In a two-dimensional layout, the bus signal lines are arranged such that adjacent signal lines are of different buses. The different buses transmit signals changed at different timings. The signal lines of the same buses transmit signals changed substantially at the same timing. Thus, cross-talk noise between signal lines can be reduced without widening a bus line pitch.

Abstract: The invention provides a communication semiconductor integrated circuit device (RF IC) capable of pulling in the frequency of a PLL circuit to a desired set frequency at high speed even in the case where a frequency settable range of the PLL circuit is wide without providing a current source other than a current source for charging and discharging in an normal operation. An oscillator as a component of a PLL circuit is constructed so as to be operative in a plurality of bands. In a state where a control voltage of the oscillator is fixed to a predetermined value, an oscillation frequency of the oscillator is measured in each of bands and stored in a storing circuit. A set value for designating a band supplied at the time of PLL operation is compared with the stored measured frequency value. From a result of comparison, a band to be actually used in the oscillator is determined, and a frequency difference between the maximum frequency of the selected band and the set frequency is obtained.