Abstract: A semiconductor integrated circuit capable of performing internal oscillation with high precision is provided. The semiconductor integrated circuit has a memory circuit, an oscillator circuit for generating an internal clock signal based on control information held in the memory circuit, a logic circuit for generating control information for causing the frequency of the internal clock signal to coincide with the frequency of an external clock signal, and an electric fuse circuit or a blow fuse circuit capable of storing the control information generated in the logic circuit and uses the internal clock signal for the synchronous operation of the internal circuit.

Abstract: The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency clock control signal to a charge pump. After lapse of a certain period (about ? of fall time), a high-frequency clock signal having a frequency higher than that of the low-frequency clock signal is output by a high-frequency clock control signal and is input as the selection clock signal to the charge pump to boost a voltage to a predetermined voltage level. In such a manner, while suppressing the peak of consumption current, the fall time of the boosted voltage can be shortened.

Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.

Abstract: The cleaning composition for removing resists includes a salt of hydrofluoric acid and a base not containing a metal (A component), a water-soluble organic solvent (B1 component), at least one organic acid or inorganic acid (C component), water (D component), and, optionally, an ammonium salt (E1 component), and having a pH 4-8. Thus, in manufacturing a semiconductor device, such as a copper interconnecting process, efficiency of removing resist residue and other etching residue after etching or ashing is improved, and corrosion resistance of a copper and an insulating film is also improved.

Abstract: A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.

Abstract: A microprocessor used in a pair with a baseband processor for performing the baseband processing, is provided with a central processing unit for calculation processing, a counter capable of measuring time in the calculation processing by the central processing unit, and an interface which enables the baseband processor to read the counter. By making the baseband processor read the counter, the processing by the baseband processor is synchronized with the processing by the central processing unit in the microprocessor. Consequently, it is possible to establish synchronization between video and voice when the video processing and the voice processing are separately performed by different processors.

Abstract: A semiconductor flash memory includes an erase/write control unit that, when performing an erase/write operation of read memory cells, reads and senses memory current of the read memory cells for each memory cell, and adjusts threshold voltage of each of the read memory cells to a predetermined value, and a readout control unit that, when performing a read operation, selects at least two read memory cells simultaneously from among the read memory cells to which the erase/write control unit stored the same data, and senses total memory current for the at least two read memory cells.

Abstract: Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.

Abstract: A radio frequency power amplifier module that brings sufficient attenuation to a radio frequency signal in a bias supply line connecting a bias control part and a radio frequency power amplifier part without increasing module substrate area is aimed. At least one bonding pad 106 having a capacitance component to a ground and stitch structure inductances 108, 109 composed of a bonding wire 105 provided via the bonding pad are provided in the bias supply line connecting the bias control part and the radio frequency power amplifier part.

Abstract: A dummy cell having a low threshold voltage is disposed in a memory cell array in alignment with a memory cell. A dummy cell with a low threshold voltage adjacent to a selected memory cell column is selected, and a source-side local bit line of the selected memory cell is coupled to a global bit line via such dummy cell. Since the source-side local bit line is coupled to a ground node at its both ends, source resistance of the memory cell can be reduced, and dependency of the source resistance of the memory cell on the position within the memory cell array can also be reduced. This allows for reducing dependency of source resistance of a memory cell on the position within the memory cell array and on the temperature in a nonvolatile semiconductor memory device.

Abstract: In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.

Abstract: As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked structure is made to have smaller dielectric constant than that at an upper-layer part thereof, and further this insulation film is a silicon oxide (SiO) film and has, in the interior thereof, nano-pores of from 0.05 nm or more to 4 nm or less in diameter as chief construction. This makes it possible to dramatically reduce effective dielectric constant while keeping the mechanical strength of the conductore layers themselves, and can materialize a highly reliable and high-performance semiconductor device having mitigated the wiring delay of signals which pass through wirings.

Abstract: A first voltage source terminal, to which a first voltage is input, is connected to a maximum voltage terminal of serially-connected secondary batteries to be monitored. A second voltage source terminal, to which a second voltage is input, is connected to a minimum voltage terminal of the secondary batteries. A battery-voltage detecting unit outputs a detection signal based on a result of a voltage monitoring. A first reference-voltage generating unit receives the first and the second voltages as operating voltages, and generates a first reference voltage. A voltage converting unit receives the detection signal, and converts the detection signal received into either the first reference voltage or the second voltage. An output terminal outputs the detection signal converted, as an output detection signal.

Abstract: A memory array including memory mats is arranged in a U shape when seen in two dimensions, and a logic circuit and an analog circuit are arranged in a region unoccupied by the memory array. This facilitates transmission of power supply voltage and signals between the peripheral circuit including the analog and logic circuits and the pad band including power supply and data pads. The analog circuit is positioned close to the power supply pad, so that voltage drop due to the resistance of power supply interconnection is restricted. It is also possible to separate a charge pumping power supply interconnection and a peripheral circuit power supply interconnection in the vicinity of the power supply pad.

Abstract: To ensure the connectability of wiring lines in a semiconductor device having terminals or reservoirs, plural terminals of a cell, which constitutes the semiconductor device, are each formed in a shape having a length corresponding to two or more lattice points. The terminals are arranged so that one or more lattice points are interposed between adjacent terminals. Among the terminals, as to terminals that are adjacent to each other in their shorter direction, it is allowable for them to partially overlap each other in their shorter direction. In this state, second-layer wiring lines are connected to the terminals via through holes, whereby reservoirs can be generated at the terminals, respectively.

Abstract: A transmitter adopting a polar loop system including a phase control loop for controlling the phase of a carrier signal outputted from a transmitting oscillator and an amplitude control loop for controlling the amplitude of a transmitting output signal outputted from a power amplification circuit, and designed to be capable of performing transmission using a GMSK modulation mode and transmission using an 8-PSK modulation mode. In the transmitter, the phase control loop is shared as a phase control loop for use in the GMSK modulation mode and a phase control loop for use in the 8-PSK modulation mode. A component similar to any one of components constituting a loop filter is provided in parallel therewith so that the component can be connected or disconnected in accordance with the modulation mode, for example, by use of a switching element.

Abstract: The occurrence of a package crack in the back vicinity of a die pad is restrained by making the outward appearance of the die pad of a lead frame smaller than that of a semiconductor chip which is mounted on it, and also the occurrence of a package crack in the main surface vicinity of the semiconductor chip is restrained by forming a layer of organic material with good adhesion property with the resin that constitutes the package body on the final passivation film (final passivation film) that covers the top layer of conductive wirings of the semiconductor chip.

Abstract: A data processing device which selects either emission of electrons from a nonvolatile memory cell or injection of electrons into it for each bit. A memory array includes a plurality of nonvolatile memory cells each having a pair of a first MOS transistor and a second MOS transistor where the first transistor has a charge retention layer and a memory gate and is used for data storage and the second transistor has a control gate and selectively connects the first transistor to a bit line. When negative voltage is applied to a memory gate, electrons held by a charge retention layer are emitted through hot carriers generated in a nonvolatile memory cell channel region for erasing; and when positive voltage is applied to the memory gate, electrons are injected into the charge retention layer through hot carriers generated in the nonvolatile memory cell channel region for writing and controls the generation and suppression of hot carriers by means of bit line voltage on each bit line.