Abstract: A communication apparatus includes a phase-locked loop circuit which receives a first signal having a frequency and converts it into an output signal having a transmission frequency and includes a current output type phase comparator which converts a phase difference between the first signal and a second signal into a current signal, a low pass filter which filters the current signal of the current output type phase comparator to produce an output signal a voltage controlled oscillator which produces an output signal having a transmission frequency corresponding to the output signal of the low pass filter the output signal of the voltage controlled oscillator constituting the output signal of the phase-locked loop circuit, a frequency converter which frequency-converts the output signal of the voltage controlled oscillator to produce the second signal, and a current source which supplies a current to an input of the low pass filter.

Abstract: The present invention relates to a structure of a capacitor, in particular using niobium pentoxide, of a semiconductor capacitor memory device. Since niobium pentoxide has a low crystallization temperature of 600° C. or less, niobium pentoxide can suppress the oxidation of a bottom electrode and a barrier metal by heat treatment. However, according to heat treatment at low temperature, carbon incorporated from CVD sources into the film is not easily oxidized or removed. Therefore, a problem that leakage current increases arises. As an insulator film of a capacitor, a layered film composed of a niobium pentoxide film and a tantalum pentoxide film, or a layered film composed of niobium pentoxide films is used. By the use of the niobium pentoxide film, the dielectric constant of the capacitor can be made high and the crystallization temperature can be made low. By multiple-stage formation of the dielectric film, leakage current can be decreased.

Abstract: Ruthenium, osmium and their oxides can be etched simply and rapidly by supplying an atomic oxygen-donating gas, typically ozone, to the aforementioned metals and their oxides through catalysis between the metals and their oxides, and the ozone without any damages to wafers and reactors and application of the catalysis not only to the etching but also to chamber cleaning ensures stable operation of reactors and production of high quality devices.

Abstract: A shading area having a transmissivity in the range of 0 to 2% is formed at the center of a clear defect in a wiring pattern of a half tone mask. Semitransparent areas having a transmissivity in the range of 10 to 25% are formed, adjacently to shading area, in areas extending from the inside of the edge of an imaginary pattern having no defect to the outside of the edge. In this way, in the correction of the defect in the half tone mask, the working accuracy tolerable margin of the correction portion of the defect can be made large.

Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

Abstract: A method of manufacturing a semiconductor integrated circuit device comprising forming a silicon oxide film as thin as 5 nm or less on the surfaces of p type wells and n type wells by wet oxidizing a substrate, heating the substrate in an atmosphere containing about 5% of an NO gas to introduce nitrogen into the silicon oxide film so as to form a silicon oxynitride film, exposing the substrate to a nitrogen plasma atmosphere to further introduce nitrogen into the silicon oxynitride film in order to form a silicon oxynitride gate insulating film having a first peak concentration near the interface with the substrate and a second peak concentration near the surface thereof. Thereby, the concentration of nitrogen in the gate insulating film is increased without raising the concentration of nitrogen near the interface between the substrate and the gate insulating film to a higher level than required.

Abstract: A semiconductor integrated circuit device for communication is provided with a PLL circuit or the like formed therein, the PLL circuit which is capable of realizing the compensation of fluctuation due to temperature change, the inhibition of increase in the chip area and the ensurement of the performance margin, and which controls a VCO having multiple oscillation frequency bands. In the case where automatic calibration is performed by switching a switch to a side of a DC voltage source in the PLL circuit using a VCO having multiple oscillation bands, a tuning voltage (Vtune) of an RFVCO is fixed to a voltage value of a DC voltage source. However, since a temperature characteristic of canceling a VCO oscillation frequency is given to the DC voltage source, it is possible to minimize the influence on the band selection when a calibration table comes to no optimum one.

Abstract: A bus system for handling changes in an access address range of a subject-of-access or a bus master is disclosed. The bus system can have an address monitor unit including a table which is shared among a plurality of bus masters and stores therein access right information. By referencing the table, the presence or absence of an access right for each of the bus masters can be determined. The table may be rewritten as appropriate to handle address range changes.

Abstract: A plurality of first sub-bit lines are each connected to a common source line via a corresponding first sub-bit line reset transistor with NMOS structure, and a plurality of second sub-bit lines are each connected to the common source line via a corresponding second sub-bit line reset transistor with NMOS structure. The plurality of first and second sub-bit line reset transistors have their respective gates receiving a sub-bit line reset signal. This sub-bit line reset signal becomes “H” for a predetermined period of time after read data is obtained during a read period.

Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.

Abstract: A method for carrying a semiconductor device includes: (a) providing semiconductor devices each having a main surface, a back surface, and a plurality of external terminals; (b) providing a tray having a front surface, a rear surface, an electronic tag imbedded in the tray, first concaved portions formed on the front surface, second concaved portions formed on the rear surface, the electronic tag constituted by a non-contact recognition type chip having a memory circuit in which recognizable information is stored, a depth of the first concaved portion is deeper than a depth of the second concaved portion; (c) housing the semiconductor devices into the first concaved portions respectively in such a manner that the back surface of the semiconductor device being oppose to a bottom of the first concaved portion; and (d) carrying the tray with the semiconductor devices.

Abstract: The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on.

Abstract: The nonvolatile semiconductor memory device of the present invention includes a memory cell array wherein data is stored in a nonvolatile state based on a difference in memory information between two memory cells comprising a memory cell pair, and a writing controller for writing data to the memory cell array. The writing controller is capable of individually setting memory information of each of the memory cells in the memory cell array.

Abstract: A semiconductor integrated circuit includes a pin section, internal circuits, an interface section, an expectation value generation circuit, a comparison circuit and a waveform generation circuit. In a first test mode, the expectation value generation circuit generates expectation values of operation signals to be generated by the interface section when first test signals having the same waveform are input via respective pins of the pin section, and the comparison circuit compares operation signals that are actually produced by the interface section with the respective expectation values and produces comparison results. In a second test mode, the waveform generation circuit supplies second test signals to the interface section, and the interface section outputs test output signals having the same waveform to the external system via respective pins of the pin section.

Abstract: The present invention provides a squelch detecting circuit capable of high-speed transfer while using a reduced number of high-speed operating operational amplifiers to reduce power consumption and the cost of parts. Input differential signals inputted to a differential amplification circuit are amplified and the amplified signal is outputted to a gain proportion circuit. The gain proportion circuit supplies a potential holding circuit with a potential proportional to the amplified signal. The potential holding circuit holds the potential supplied from the gain proportion circuit. A comparator circuit compares the potential held by the potential holding circuit with a reference potential to decide whether it is a squelch state or a non-squelch state and outputs the result as a detect signal.

Abstract: The invention provides a semiconductor chip manufacturing method, including a step of forming a front-surface-side concave portion in a semiconductor substrate having a front surface and a rear surface, a functional device being formed on the front surface, the front-surface-side concave portion being formed in the front surface and having a predetermined depth smaller than a thickness of the semiconductor substrate; a dummy plug forming step of supplying nonmetallic material into the front-surface-side concave portion and embedding a dummy plug made of the nonmetallic material; a thinning step of removing a part of the rear surface of the substrate and thinning the semiconductor substrate so that the thickness of the semiconductor substrate becomes smaller than the depth of the front-surface-side concave portion and so that the front-surface-side concave portion is formed into a through-hole; a dummy plug removing step of removing the dummy plug; and a step of supplying metallic material into the through-hol

Abstract: A memory cell includes a selective gate and a memory gate arranged on one side surface of the selective gate. The memory gate includes one part formed on one side surface of the selective gate and the other part electrically isolated from the selective gate and a p-well through an ONO layer formed below the memory gate. A sidewall-shaped silicon oxide is formed on side surfaces of the selective gate, and a sidewall-shaped silicon dioxide layer and a silicon dioxide layer are formed on side surfaces of the memory gate. The ONO layer formed below the memory gate is terminated below the silicon oxide, and prevents generation of a low breakdown voltage region in the silicon oxide near an end of the memory gate during deposition of the silicon dioxide layer.

Abstract: For improving the filling properties between vertical MISFETs constituting a SRAM memory cell, the vertical MISFETs are formed over horizontal drive MISFETs and transfer MISFETs, and they are disposed with a narrow pitch in the Y direction and a wide pitch in the X direction. After a first insulating film (O3-TEOS) having good coverage is disposed over columnar laminates having a lower semiconductor layer, an intermediate semiconductor layer, an upper semiconductor layer and a silicon nitride film and a gate electrode formed over the side walls of the laminates via a gate insulating film to completely fill a narrow pitch space, a second insulating film (HDP silicon oxide film) is deposited over the first insulating film, resulting in an improvement in the filling properties, even in a narrow pitch portion, between vertical MISFETs having a high aspect ratio.

Abstract: With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n+ type semiconductor regions, each having a conduction type opposite to p+ type semiconductor regions for a source and drain of a high breakdown voltage pMIS, are disposed in a boundary region between each of trench type isolation portions at both ends, in a gate width direction, of a channel region of the high breakdown voltage pMIS and a semiconductor substrate at positions spaced away from p? type semiconductor regions, each having a field relaxing function, of the high breakdown voltage pMIS, so as not to contact the p? type semiconductor regions (on the drain side, in particular). The n+ type semiconductor regions extend to positions deeper than the trench type isolation portions.

Abstract: It is aimed at improving the efficiency of data transfer processing and the concurrent data processing on a central processing unit. A data transfer device can independently request a bus access right and output an address to a first bus (IBUS) and a second bus (PBUS). It is possible to solve the state of competing for the bus access right between both buses. While the bus access right of one bus is granted for reading or writing, the bus access right of the other bus can be released. When the data transfer device releases the bus access right for the first bus, a central processing unit can process data. In response to one data transfer start request, the bus access right is requested for one bus and the other bus, There is not used a sequence of requesting the bus access right in response to different data transfer requests for respective buses. It is possible to simplify a handshake sequence of a data transfer request and its acknowledgment.