Abstract: The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.

Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.

Abstract: Miniaturization and high-performance of a semiconductor device are promoted, which has a package on package (POP) structure in which a plurality of semiconductor packages is stacked in a multistage manner. A testing conductive pad for determining the quality of a conduction state of a microcomputer chip and a memory chip is arranged outside a conductive pad for external input/output and thereby the route of a wire that couples the microcomputer chip and the memory chip to the testing conductive pad is reduced in length. Further, the wire that couples the microcomputer chip and the memory chip to the testing conductive pad is coupled to a pad in the outer row among conductive pads in two rows to be coupled to the microcomputer chip.

Abstract: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate, and insulating layer on the semiconductor substrate, a plurality of contact plugs in the insulating layer, and an insulating layer where capacitors, a plurality of contact plugs, barrier metal layers and copper interconnections are formed. Source/drain regions in the upper surface of the semiconductor substrate are electrically connected to the copper interconnections. One of adjacent source/drain regions in the upper surface of the semiconductor substrate is electrically connected to the copper interconnection, while the other is electrically connected to the capacitor.

Abstract: A RISC data processor in which the number of flags generated by each instruction is increased so that a decrease of flag-generating instructions exceeds an increase of flag-using instructions in quantity, thereby achieving the decrease in instructions. An instruction for generating flags according to operands' data sizes is defined, and an instruction set handled by the RISC data processor includes an instruction capable of executing an operation on operands in more than one data size. An identical operation process is conducted on the small-size operand and on low-order bits of the large-size operand, and flags are generated capable of coping with the respective data sizes regardless of the data size of each operand subjected to the operation. Thus, a reduction in instruction code space of the RISC data processor can be achieved.

Abstract: A digital-correction-type A/D converter which is a charge sharing type and performing successive approximation is realized in a small area. The A/D converter is configured with an A/D conversion unit which is a charge sharing type and performing successive approximation, a digital correction unit which receives a digital output of the A/D conversion unit and performs digital correction to the digital output, and a holding unit which holds a test signal. A test signal of a common value from the holding unit is inputted into the A/D conversion unit in the first period and the second period. The A/D conversion correction coefficient for the digital correction unit is calculated on the basis of the digital correction result of the digital correction unit in the first period, and the digital correction result of the digital correction unit in the second period.

Abstract: In a display driver, a first backlight control unit using a histogram and a second backlight control unit using an optical sensor can be used in combination. The display driver includes a PWM generating unit setting a control signal value consisting of a product of a luminance rate of X % and a luminance rate of Y % as a luminance rate of a control signal for controlling a backlight with respect to maximum backlight luminance when a luminance rate of a control signal obtained by first backlight control with respect to the maximum backlight luminance is X % and a luminance rate of a control signal obtained by second backlight control with respect to the maximum backlight luminance is Y %.

Abstract: A semiconductor device includes a substrate, an internal circuit including a plurality of transistors provided over the substrate, an insulating film provided over the substrate, a bonding pad provided over the insulating film, an inductor being formed in the insulating film, the inductor carrying out a signal transmission/reception to/from an external device in a non-contact manner by an electromagnetic induction and being electrically coupled to the internal circuit. The inductor includes a first conducting layer, and the bonding pad includes a second conducting layer. The first conducting layer includes a lower level layer than the second conducting layer in a thickness direction of the substrate. Ina plan view, the inductor includes a first portion overlapping the bonding pad and a second portion not overlapping the bonding pad.

Abstract: To improve reliability of a semiconductor device obtained through a dicing step. In a ring region, a first outer ring is provided outside a seal ring, and a second outer ring is provided outside the first outer ring. This can prevent a crack from reaching even the seal ring that exists in the ring region, for example, when a scribe region located outside the ring region is cut off by a dicing blade.

Abstract: In a semiconductor device including a memory cell array formed of memory cells using a storage element by a variable resistor and a select transistor, a buffer cell is arranged between a sense amplifier and the memory cell array and between a word driver and the memory cell array. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.

Abstract: A semiconductor device includes a semiconductor chip having a first main surface, a second main surface opposite to the first main surface, a side surface arranged between the first main surface and the second main surface, and a magnetic storage device, a first magnetic shield overlaying on the first main surface, a second magnetic shield overlaying on the second main surface, and a third magnetic shield overlaying on the side surface. The first and second magnetic shields are mechanically connected via the third magnetic shield.

Abstract: When graphics computations are to be performed to calculate the display data of a figure to be drawn within a frame that is formed of a plurality of lines in accordance with input vector data, the present invention reduces the storage capacity of a RAM to which a work area for storing intermediate data is allocated. When the graphics computations are to be performed, the frame in which the figure is to be displayed is segmented into a plurality of drawing areas for each of the lines. As regards the work area for storing the intermediate data, the same work area is allocated to all the drawing areas. The graphics computations for calculating the intermediate data of the individual drawing areas are sequentially performed by repeatedly using the same work area.

Abstract: To enhance the performance of a semiconductor device. In a method for manufacturing a semiconductor device, a metal film is formed over a semiconductor substrate having an insulating film formed on a surface thereof, and then the metal film is removed in a memory cell region, whereas, in a part of a peripheral circuit region, the metal film is left. Next, a silicon film is formed over the semiconductor substrate, then the silicon film is patterned in the memory cell region, and, in the peripheral circuit region, the silicon film is left so that an outer peripheral portion of the remaining metal film is covered with the silicon film. Subsequently, in the peripheral circuit region, the silicon film, the metal film, and the insulating film are patterned for forming an insulating film portion formed of the insulating film, a metal film portion formed of the metal film, and a conductive film portion formed of the silicon film.

Abstract: A pMIS region is provided between a boundary extending in a first direction and passing through each of a plurality of standard cells and a first peripheral edge. An nMIS region is provided between the boundary and a second peripheral edge. A power supply wiring and a grounding wiring extend along the first and second peripheral edges, respectively. A plurality of pMIS wirings and a plurality of nMIS wirings are arranged on a plurality of first virtual lines and a plurality of second virtual lines, respectively, extending in the first direction and arranged with a single pitch in a second direction. The first virtual line that is the closest to the boundary and the second virtual line that is the closest to the boundary have therebetween a spacing larger than the single pitch.

Abstract: A power supply topology is used in which a transistor is provided on the side of an output node of a rectifying circuit. An inductor is provided on the side of a reference node, a resistor is inserted between the transistor and the inductor, and one end of the resistor is coupled to a ground power supply voltage of a PFC circuit. The PFC circuit includes a square circuit which squares a result of multiplication of an input voltage detection signal and feedback information (output voltage of an error amplifier circuit). The PFC circuit drives on the transistor when a detection voltage developed at the resistor reaches zero, and drives off the transistor when the detection signal reaches an output signal of the square circuit.

Abstract: A communication device includes: an amplifier (62) arranged to amplify a reception signal received from one of the plurality of terminals; a first demodulation unit (26) arranged to demodulate a first frame transmitted using a first communication method operable to communicate when CNR is smaller than 0 dB; a second demodulation unit (27) arranged to demodulate, in parallel with the first demodulation unit demodulating the first frame, a second frame transmitted using a second communication method having a rate higher than a rate of the first communication method at a frequency band same as a frequency band used for the first communication method; and a gain controller (64) arranged to adjust a gain of the amplifier in accordance with a detection outcome of a preamble included in the first frame and the second frame.

Abstract: The controller LSI is connected to an SPI flash memory having a deep power down mode (DPM), and brings the SPI flash memory to the DPM and then brings itself to low power consumption mode (LPM) that volatilizes data in a RAM. This invention solves the problem that the controller LSI cannot release the peripheral device from the DPM upon returning from the LPM due to the volatilization of the data. The controller LSI includes a CPU, the RAM, and an SPI control unit transmitting an SPI command to the flash memory. The SPI command includes a power down command to bring the flash memory into DPM and a release command to release it from the DPM. Upon returning from the LPM, the controller LSI causes the control unit to transmit a release command to the flash memory irrespective of whether it is in DPM or normal mode.

Abstract: Techniques capable of improving the yield of IGBTs capable of reducing steady loss, turn-off time, and turn-off loss are provided. Upon formation of openings in an interlayer insulting film formed on a main surface of a substrate, etching of a laminated insulating film of a PSG film and an SOG film and a silicon oxide film is once stopped at a silicon nitride film. Then, the silicon nitride film and the silicon oxide film are sequentially etched to form the openings. As a result, the openings are prevented from penetrating through an n-type source layer and a p+-type emitter layer having a thickness of 20 to 100 nm and reaching the substrate.

Abstract: A control logic unit generates a control signal which is activated while a power supply normally operates. A charge circuit is connected to a first node on a voltage control line supplied with a voltage generated by a voltage generation circuit, so that its capacitive element is charged with electric charge. A first discharge circuit is connected to a charge storage node of the charge circuit and discharges the stored electric charge when the control signal is activated. A second discharge circuit discharges the first node when the charge storage node has a potential exceeding a predetermined potential.

Abstract: In an internal voltage generation circuit, four charge pump circuits are provided, the first two charge pump circuits are driven with a long period at the time of standby mode, and the four charge pump circuits are driven with a short period at the time of active mode. Therefore, a layout area can be reduced compared with a case where a charge pump circuit for standby mode and a charge pump circuit for active mode are provided separately.