Patents Assigned to RENESAS
  • Publication number: 20140237214
    Abstract: This present invention provides a fast data transfer for a concurrent transfer of multiple ROI areas between an internal memory array and a single memory where each PE can specify the parameter set for the area to be transferred independently from the other PE. For example, for a read transfer, the requests are generated in a way that first the first element of each ROI area is requested from the single memory for each PE before the following elements of each ROI area are requested. After the first element from each ROI area has been received from the single memory in a control processor and has been transferred from the control processor over a bus system to the internal memory array, all elements are in parallel stored to the internal memory array. Then, the second element of each ROI area is requested from the single memory for each PE. The transfer finishes after all elements of each ROI area are transferred to their assigned PEs.
    Type: Application
    Filed: September 27, 2011
    Publication date: August 21, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Hanno Lieske
  • Publication number: 20140225174
    Abstract: By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall. Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating. At least any of the upper antireflection coating and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other.
    Type: Application
    Filed: April 21, 2014
    Publication date: August 14, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Akie YUTANI, Yasutaka Nishioka
  • Publication number: 20140226049
    Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.
    Type: Application
    Filed: April 18, 2014
    Publication date: August 14, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroto UTSUNOMIYA, Katsumi DOSAKA, Hiroshi KATO, Fukashi MORISHITA, Fumiyasu SASAKI
  • Publication number: 20140225240
    Abstract: To suppress the reduction in reliability of a resin-sealed semiconductor device. A first cap (member) and a second cap (member) with a cavity (space formation portion) are superimposed and bonded together to form a sealed space. A semiconductor including a sensor chip (semiconductor chip) and wires inside the space is manufactured in the following way. In a sealing step of sealing a joint part between the caps, a sealing member is formed of resin such that an entirety of an upper surface of the second cap and an entirety of a lower surface of the first cap are respectively exposed. Thus, in the sealing step, the pressure acting in the direction of crushing the second cap can be decreased.
    Type: Application
    Filed: April 18, 2014
    Publication date: August 14, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Noriyuki TAKAHASHI
  • Publication number: 20140225189
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: April 23, 2014
    Publication date: August 14, 2014
    Applicants: RENESAS ELECTRONICS CORPORATION, HITACHI ULSI SYSTEMS CO., LTD.
    Inventors: Sumito NUMAZAWA, Yoshito NAKAZAWA, Masayoshi KOBAYASHI, Satoshi KUDO, Yasuo IMAI, Sakae KUBO, Takashi SHIGEMATSU, Akihiro OHNISHI, Kozo UESAWA, Kentaro OISHI
  • Publication number: 20140225221
    Abstract: A semiconductor device includes a semiconductor chip including a main surface, an internal circuit including a plurality of transistors, formed on the main surface, a bonding pad electrically connected to the internal circuit, formed on the main surface, an inductor for communicating an external device in a non-contact manner, formed on the main surface, and a seal ring formed along an outer peripheral edge of the semiconductor chip to surround the internal circuit and the bonding pad in a plan view. The inductor has a configuration to surround the internal circuit and the bonding pad in the plan view and along the seal ring. The inductor is arranged inside the seal ring.
    Type: Application
    Filed: April 17, 2014
    Publication date: August 14, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Yasutaka Nakashiba
  • Publication number: 20140217582
    Abstract: This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate.
    Type: Application
    Filed: April 9, 2014
    Publication date: August 7, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinji BABA, Toshihiro IWASAKI, Masaki WATANABE
  • Publication number: 20140220740
    Abstract: Grooves are formed on the front surfaces of first and second semiconductor wafers each including an aggregate of a plurality of semiconductor chips. The grooves each extend on a dicing line set between the semiconductor chips and to have a larger width than the dicing line. Thereafter the first and second semiconductor wafers are arranged so that the front surfaces thereof are opposed to each other, and the space between the first semiconductor wafer and the second semiconductor wafer is sealed with underfill. Thereafter the rear surfaces of the first and second semiconductor wafers are polished until at least the grooves are exposed, and a structure including the first and second semiconductor wafers and the underfill is cut on the dicing line.
    Type: Application
    Filed: April 9, 2014
    Publication date: August 7, 2014
    Applicants: ROHM CO., LTD., RENESAS ELECTRONICS CORPORATION
    Inventors: Tadahiro MORIFUJI, Haruo SHIMAMOTO, Chuichi MIYAZAKI, Toshihide UEMATSU, Yoshiyuki ABE
  • Publication number: 20140219010
    Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
    Type: Application
    Filed: April 4, 2014
    Publication date: August 7, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Masanao Yamaoka, Koichiro Ishibashi, Shigezumi Matsui, Kenichi Osada
  • Publication number: 20140206155
    Abstract: The reliability of a semiconductor device including a MOSFET formed over an SOI substrate is improved. A manufacturing method of the semiconductor device is simplified. A semiconductor device with n-channel MOSFETsQn formed over an SOI substrate SB includes an n+-type semiconductor region formed as a diffusion layer over an upper surface of a support substrate under a BOX film, and a contact plug CT2 electrically coupled to the n+-type semiconductor region and penetrating an element isolation region, which can control the potential of the support substrate. At a plane of the SOI substrate SB, the n-channel MOSFETsQn each extend in a first direction, and are arranged between the contact plugs CT2 formed adjacent to each other in the first direction.
    Type: Application
    Filed: March 20, 2014
    Publication date: July 24, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Komaki INOUE, Yutaka HOSHINO
  • Publication number: 20140203364
    Abstract: A semiconductor device having an n channel MISFET formed on an SOI substrate including a support substrate, an insulating layer formed on the support substrate and a silicon layer formed on the insulating layer has the following structure. An impurity region for threshold adjustment is provided in the support substrate of a gate electrode so that the silicon layer contains carbon. The threshold value can be adjusted by the semiconductor region for threshold adjustment in this manner. Further, by providing the silicon layer containing carbon, even when the impurity of the semiconductor region for threshold adjustment is diffused to the silicon layer across the insulating layer, the impurity is inactivated by the carbon implanted into the silicon layer. As a result, the fluctuation of the transistor characteristics, for example, the fluctuation of the threshold voltage of the MISFET can be reduced.
    Type: Application
    Filed: January 15, 2014
    Publication date: July 24, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Takaaki TSUNOMURA, Toshiaki IWAMATSU
  • Publication number: 20140199831
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Application
    Filed: March 16, 2014
    Publication date: July 17, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Katsuhiko HOTTA, Kyoko SASAHARA
  • Publication number: 20140198735
    Abstract: Apparatus and method for communication are provided. The solution includes controlling the communication of a transceiver on shared data channels using a data channel slot including a sensing period and a data period and controlling a transceiver to communicate on common and dedicated control channels on a shared spectrum using control channel slots, each control channel slot including a downlink part and an uplink part, wherein the uplink part occurs at the same time as the sensing period of a data channel slot.
    Type: Application
    Filed: March 25, 2013
    Publication date: July 17, 2014
    Applicant: RENESAS MOBILE COPORATION
    Inventors: Timo K. KOSKELA, Sami Jukka HAKOLA, Samuli TURTINEN, Anna PANTELIDOU
  • Publication number: 20140198577
    Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.
    Type: Application
    Filed: March 16, 2014
    Publication date: July 17, 2014
    Applicants: HITACHI ULSI SYSTEMS CO., LTD., RENESAS ELECTRONICS CORPORATION
    Inventors: Toshihiro TANAKA, Yukiko UMEMOTO, Mitsuru HIRAKI, Yutaka SHINAGAWA, Masamichi FUJITO, Kazufumi SUZUKAWA, Hiroyuki TANIKAWA, Takashi YAMAKI, Yoshiaki KAMIGAKI, Shinichi MINAMI, Kozo KATAYAMA, Nozomu MATSUZAKI
  • Publication number: 20140191309
    Abstract: When forming a super junction by the embedded epitaxial method, adjusting a taper angle of dry etching to form an inclined column is generally performed in trench forming etching, in order to prevent a reduction in breakdown voltage due to fluctuations in concentration in an embedded epitaxial layer. However, according to the examination by the present inventors, it has been made clear that such a method makes design more and more difficult in response to the higher breakdown voltage. In the present invention, the concentration in an intermediate substrate epitaxy column area in each substrate epitaxy column area configuring a super junction is made more than that in other areas within the substrate epitaxy column area, in a vertical power MOSFET having the super junction by the embedded epitaxial method.
    Type: Application
    Filed: December 17, 2013
    Publication date: July 10, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Satoshi EGUCHI, Yoshito NAKAZAWA, Tomohiro TAMAKI
  • Publication number: 20140191737
    Abstract: A power-supply apparatus according to an aspect includes an inductor, a transistor that supplies, in an on-state, a current to the input side of the inductor, a second transistor that becomes, when the first transistor is in an off-state, an on-state and thereby brings the input side of the inductor to a predetermined potential, a signal generation unit that generates voltage signals corresponding to a current flowing to the inductor, an amplifier that outputs a current according to the voltage signals, a converter that converts the current output from the amplifier into a voltage signal, and a control unit that controls the transistors based on a first feedback signal corresponding to the voltage on the output side of the inductor and the voltage signal, which is used as a second feedback signal.
    Type: Application
    Filed: December 4, 2013
    Publication date: July 10, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshio NAGASAWA, Yoshitaka ONAYA, Koji SAIKUSA, Shin CHIBA
  • Publication number: 20140191338
    Abstract: In a region just below an access gate electrode in an SRAM memory cell, a second halo region is formed adjacent to a source-drain region and a first halo region is formed adjacent to a first source-drain region. In a region just below a drive gate electrode, a third halo region is formed adjacent to the third source-drain region and a fourth halo region is formed adjacent to a fourth source-drain region. The second halo region is set to have an impurity concentration higher than the impurity concentration of the first halo region. The third halo region is set to have an impurity concentration higher than the impurity concentration of the fourth halo region. The impurity concentration of the first halo region and the impurity concentration of the fourth halo region are different from each other.
    Type: Application
    Filed: July 29, 2011
    Publication date: July 10, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Kengo Masuda
  • Publication number: 20140191363
    Abstract: An external storage device including an interconnect substrate having a contact type external terminal, at least one semiconductor chip disposed over a first surface of the interconnect substrate, and a sealing resin layer which seals the at least one semiconductor chip and does not cover the external terminal. The at least one semiconductor chip includes a storage device, an inductor being connected to the storage device, a driver circuit configured to control the inductor and an interconnect layer. The interconnect layer is formed at a first surface of the semiconductor chip and includes the inductor. The first surface of the semiconductor chip is other than facing the first surface of the interconnect substrate, and the inductor and the driver circuit are connected to each other through the interconnect layer.
    Type: Application
    Filed: March 10, 2014
    Publication date: July 10, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasutaka Nakashiba, Kenta Ogawa
  • Publication number: 20140187047
    Abstract: A method for forming a semiconductor device that includes a SiARC layer formed over a photoresist film which is formed over spacer portions which are formed on a spacer assist layer which is formed over a hard mask layer. The SiARC layer has an etch rate substantially similar to the etch rate of the spacer assist layer. The photoresist layer and the SiARC layer are removed from a first region to expose the spacer portions and the spacer assist layer. The SiARC layer in the second region and the exposed spacer assist layer in the first region are simultaneously etched leaving remaining spacer portions and remaining spacer assist layer portions. A part of the hard mask layer is etched to form hard mask portions in the first region using the remaining spacer portions and the remaining spacer assist layer portions as an etching mask.
    Type: Application
    Filed: December 26, 2013
    Publication date: July 3, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Masayoshi TAGAMI, Naoya INOUE
  • Publication number: 20140177699
    Abstract: An equalizer includes a first discrimination circuit to receive an input signal corresponding to a signal output from a transmit-side equalizer to binarize the input signal by a first threshold value in unit time, a second discrimination circuit to binarize the input signal by a second threshold value in unit time, a first delay circuit to delay an output signal of the first discrimination circuit and that includes N-number (N>=2) of stages of unit delay circuits connected in cascade and operating in unit time, a second delay circuit to receives an output signal of the second discrimination circuit and that includes not less than an (N+1)-number of stages of unit delay circuits connected in cascade and operating in unit time, and a control unit that receives an output of the first delay circuit, and a second output signal output from the second delay circuit.
    Type: Application
    Filed: December 18, 2013
    Publication date: June 26, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Kenzo TAN, Masahiro TAKEUCHI