Patents Assigned to RENESAS
  • Patent number: 9041314
    Abstract: A power supply topology is used in which a transistor is provided on the side of an output node of a rectifying circuit. An inductor is provided on the side of a reference node, a resistor is inserted between the transistor and the inductor, and one end of the resistor is coupled to a ground power supply voltage of a PFC circuit. The PFC circuit includes a square circuit which squares a result of multiplication of an input voltage detection signal and feedback information (output voltage of an error amplifier circuit). The PFC circuit drives on the transistor when a detection voltage developed at the resistor reaches zero, and drives off the transistor when the detection signal reaches an output signal of the square circuit.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: May 26, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Ryosei Makino, Kenichi Yokota, Tomohiro Tazawa
  • Patent number: 9040358
    Abstract: A semiconductor device permitting the reduction of cost is disclosed. In a semiconductor package wherein electrode pads of a semiconductor chip and corresponding inner leads are electrically coupled with each other through a plurality of bonding wires, sensing wires (second and fourth bonding wires) are made thinner than other bonding wires (first and third bonding wires) coupled to inner leads same as those with the sensing wires coupled thereto, thereby reducing the cost of gold wires to attain the reduction in cost of the semiconductor package.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: May 26, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuya Fukuhara, Kiyonori Yoshitomi, Takehiko Ikegami, Yujiro Kawasoe
  • Patent number: 9041455
    Abstract: A semiconductor device prevents recognition failure in mutual recognition between a host and a device compliant with USB Specifications. The semiconductor device includes: an interterminal opening/closing section having a plurality of first conductivity type MOS transistors, the respective sources or drains of which are cascaded, in which the source or drain of a first-stage MOS transistor among the cascaded MOS transistors is used as a first terminal, the source or drain of a final-stage MOS transistor among the cascaded MOS transistors is used as a second terminal, and the respective gates of the cascaded MOS transistors receive a control signal for controlling the opening or short-circuiting between the first and second terminals; and a current bypass section that reduces a current flowing into either one connection node coupling the respective sources or drains of the cascaded MOS transistors.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: May 26, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tomofumi Higashide
  • Patent number: 9035392
    Abstract: A pMIS region is provided between a boundary extending in a first direction and passing through each of a plurality of standard cells and a first peripheral edge. An nMIS region is provided between the boundary and a second peripheral edge. A power supply wiring and a grounding wiring extend along the first and second peripheral edges, respectively. A plurality of pMIS wirings and a plurality of nMIS wirings are arranged on a plurality of first virtual lines and a plurality of second virtual lines, respectively, extending in the first direction and arranged with a single pitch in a second direction. The first virtual line that is the closest to the boundary and the second virtual line that is the closest to the boundary have therebetween a spacing larger than the single pitch.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: May 19, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Nobuhiro Tsuda, Hidekatsu Nishimaki, Hiroshi Omura, Yuko Yoshifuku
  • Patent number: 9035404
    Abstract: A semiconductor device includes a substrate, a multilayer wiring layer formed over the substrate, an MTJ (Magnetic Tunnel Junction) element formed in an insulating layer located lower than an uppermost wiring layer in the multilayer wiring layer, a wiring formed in a wiring layer immediately above the MTJ element and coupled to the MTJ element, and a shield conductor region provided in the wiring or a wiring layer immediately above the wiring, and covering an entirety of the MTJ element in a plan view.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: May 19, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshihisa Matsubara
  • Patent number: 9035450
    Abstract: A semiconductor substrate includes a semiconductor chip and an interconnect substrate. The interconnect substrate has an interconnect region between a first main surface formed with plural orderly arranged first and second signal electrodes connected to the semiconductor chip, and a second main surface. The interconnect region has a core substrate, interconnect layers formed on both surfaces thereof, plural first through holes and plural first vias that pass through the interconnect layer on the side of the first main surface for forming impedance matching capacitances. Each first through hole is connected to a first signal interconnect at a position spaced part from the first signal electrode by a first interconnect length and each first via is connected to the second signal interconnect at a position spaced apart from the second signal electrode by a second interconnect length that is substantially equal with the first interconnect length.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: May 19, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shuuichi Kariyazaki, Ryuichi Oikawa
  • Patent number: 9035360
    Abstract: A semiconductor device includes a logic circuit and an active element circuit. The logic circuit is provided with semiconductor elements formed in a semiconductor substrate. The active element circuit is provided with transistors formed using semiconductor layers formed over a diffusion insulating film formed above a semiconductor substrate. The active element circuit is controlled by the logic circuit.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: May 19, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kishou Kaneko, Naoya Inoue, Yoshihiro Hayashi
  • Patent number: 9034740
    Abstract: The deposition rate of a porous insulation film is increased, and the film strength of the porous insulation film is improved. Two or more organic siloxane raw materials each having a cyclic SiO structure as a main skeleton thereof, and having mutually different structures, are vaporized, and transported with a carrier gas to a reactor (chamber), and an oxidant gas including an oxygen atom is added thereto. Thus, a porous insulation film is formed by a plasma CVD (Chemical Vapor Deposition) method or a plasma polymerization method in the reactor (chamber). In the step, the ratio of the flow rate of the added oxidant gas to the flow rate of the carrier gas is more than 0 and 0.08 or less.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: May 19, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hironori Yamamoto, Fuminori Ito, Yoshihiro Hayashi
  • Patent number: 9036093
    Abstract: A semiconductor device includes a one-segment tuner I/F that is connected to a one-segment tuner, a tuner I/F that is connected to a digital terrestrial tuner, a decoder that selectively decodes a first broadcast signal supplied from the one-segment tuner I/F and a second broadcast signal supplied from the tuner I/F, a general purpose processor that is provided separately from the decoder and decodes the first broadcast signal, and a switch unit that, based on signal intensity of the second broadcast wave, switches the decoding by the decoder between the first broadcast signal and the second broadcast signal while the general purpose processor is decoding the first broadcast signal. The one-segment tuner I/F, the tuner I/F, the decoder, the general purpose processor, and the switch unit are integrated on one chip.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: May 19, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshihiko Hotta, Seiichi Saito, Kazushige Yamagishi
  • Patent number: 9035460
    Abstract: To provide a technique adopting a TSV technique, capable of improving manufacturing yield and reliability of semiconductor devices. By partitioning a connection pad-forming region into a plurality of regions and by forming, respectively, connection pads 17 having a relatively small planar area, spaced apart from an adjacent connection pad 17 in each of partitioned regions, dishing generated in the connection pad 17 is lightened. In addition, by not forming a through hole 23 for forming a through electrode 27 in an interlayer insulating film 9 covering a semiconductor element, intrusion of H2O, a metal ion such as Na+ or K+, etc. into an element-forming region from the through hole, via the interlayer insulating film is prevented.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: May 19, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masazumi Matsuura
  • Publication number: 20150131384
    Abstract: In a nonvolatile memory device (4) provided in a semiconductor device, when data is erased based on a band-to-band tunneling scheme, supply of a boosted voltage to a memory cell (MC) to be erased is ended when a condition that an output voltage (VUCP) of a charge pump circuit (52) has recovered to a predetermined reference voltage is satisfied and additionally a condition that a predetermined reference time has elapsed since start of supply of the boosted voltage (VUCP) to the memory cell (MC) to be erased is satisfied.
    Type: Application
    Filed: August 29, 2012
    Publication date: May 14, 2015
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Tomoya Ogawa, Takashi Ito, Mitsuhiro Tomoeda
  • Publication number: 20150125969
    Abstract: First, a product to be inspected is prepared. The product to be inspected includes a substrate and a first film formed on the substrate. TDS is performed while the temperature of the product to be inspected is raised to 1,000° C. or higher, and the quality of the product to be inspected is determined by checking for the presence or absence of a peak at 1,000° C. or higher. Meanwhile, the substrate is, for example, a semiconductor substrate such as a silicon substrate. In addition, the rate of temperature rise is, for example, equal to or higher than 40° C./min and equal to or lower than 80° C./min. The upper limit of the temperature of TDS is, for example, 1,300° C.
    Type: Application
    Filed: November 3, 2014
    Publication date: May 7, 2015
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Shien CHO, Takahiro HARA, Kenichi ITO
  • Publication number: 20150124138
    Abstract: Provided is a solid-state image sensing device that performs an A/D conversion operation at high speed. A sample-and-hold section 12 included in an A/D converter in a CMOS image sensor includes switches S1a and S1b and capacitor C1 that sample and hold a dark signal during each cycle period, switches S2a and S2b and capacitor C2 that sample and hold a bright signal during an odd-numbered cycle period, and switches S3a and S3b and capacitor C3 that sample and hold a bright signal during an even-numbered cycle period. While a bright signal is held with switch S2b placed in a conducting state, the next bright signal can be sampled by placing switch S3a in a conducting state.
    Type: Application
    Filed: October 20, 2014
    Publication date: May 7, 2015
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuhiro UEDA, Shunsuke OKURA, Fukashi MORISHITA
  • Publication number: 20150115410
    Abstract: A plurality of first wiring layers are arranged on a main surface of a substrate, a first insulating film is arranged on upper faces of the plurality of first wiring layers, a second insulating film is arranged on an upper face of the first insulating film, and a plurality of second wiring layers are arranged on the second insulating film. A metal resistive element layer is arranged just below at least one second wiring layer among the plurality of second wiring layers. A plurality of conductive layers extend from the plurality of second wiring layers respectively to the metal resistive element layer in a Z direction perpendicular to the main surface. The metal resistive element layer includes a metal wiring layer. At least one part of a side face of at least one conductive layer among the plurality of conductive layers is connected to the metal wiring layer.
    Type: Application
    Filed: October 17, 2014
    Publication date: April 30, 2015
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Shigeo TOKUMITSU, Takahiro MORI, Tetsuya NITTA
  • Publication number: 20150115359
    Abstract: In a semiconductor device, a lightly doped second semiconductor layer of a first conductive type is joined with a heavily doped first semiconductor layer of the first conductive type. A power transistor having a first conductive type channel and a transistor are formed in surface regions of the second semiconductor layer, respectively. A first diffusion layer of a second conductive type is formed in a surface region of the second semiconductor layer to provide a boundary between the power transistor and the transistor. The first semiconductor layer functions as a drain of the power transistor. The first diffusion layer region is set to the same voltage as that of the drain.
    Type: Application
    Filed: October 28, 2014
    Publication date: April 30, 2015
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Akio TAMAGAWA, Makoto TANAKA
  • Publication number: 20150113210
    Abstract: There is provided a data storage flash memory management method that does not require a management area and can reduce an access load. A data storage flash memory management method for storing k time-varying parameters (k is a positive integer) in a flash memory including j blocks (j is an even number not less than 2) as erase units is configured as follows. The j blocks are divided into two areas which are a primary macroblock and a secondary macroblock, each including j/2 blocks. Each of the primary macroblock and the secondary macroblock is divided into k or more segments each having an equal memory capacity, with one of the macroblocks as an active system and the other as a standby system. The k parameters are one-to-one associated with k segments of the k or more segments, and each parameter is written or read to/from a corresponding segment in an active-system macroblock.
    Type: Application
    Filed: October 8, 2014
    Publication date: April 23, 2015
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi SUZUKI, Ryosuke YAMAUCHI
  • Publication number: 20150109155
    Abstract: To suppress detection accuracy of a measurement resistance from decreasing by an on-resistance of a selector switch. The selector switch is provided between a first node coupled to a first voltage through a reference resistance and multiple second nodes coupled to the second voltage through measurement resistances, and selects the second node to be coupled to the first node with the selector switch. A correction circuit generates a voltage obtained by adding the second voltage to a voltage between the second node and the first node as a correction voltage. A double integral ADC finds a first integral time elapsed when a difference voltage of the correction voltage to a voltage of the first node is integrated to the first voltage and a second integral time elapsed when the difference voltage of the first voltage to the voltage of the first node is integrated to the correction voltage.
    Type: Application
    Filed: October 6, 2014
    Publication date: April 23, 2015
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Masumi KON, Jou KUDOU
  • Publication number: 20150108541
    Abstract: A semiconductor device in which short circuit capability can be improved while decline in overall current capability is suppressed. In the semiconductor device, a plurality of IGBTs (insulated gate bipolar transistors) arranged in a row in one direction over the main surface of a semiconductor substrate include an IGBT located at an extreme end in the one direction and an IGBT located more centrally than the IGBT located at the extreme end. The current capability of the IGBT located at the extreme end is higher than the current capability of the IGBT located centrally.
    Type: Application
    Filed: September 29, 2014
    Publication date: April 23, 2015
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Mikio TSUJIUCHI, Tetsuya NITTA
  • Publication number: 20150103950
    Abstract: In a semiconductor device, a transmitting circuit generates a delayed data signal and a first delayed retransmission request signal by delaying a data signal and a first retransmission request signal, respectively, and outputs a pulse signal at an edge of the delayed data signal and the first delayed retransmission request signal and prohibits output of the pulse signal at an edge of the first delayed retransmission request signal during a specified period across an edge of the delayed data signal.
    Type: Application
    Filed: December 18, 2014
    Publication date: April 16, 2015
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Shunichi KAERIYAMA
  • Publication number: 20150084209
    Abstract: A semiconductor device has a chip mounting part, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip is mounted over the chip mounting part in a direction in which its first principal plane faces the chip mounting part. A part of the second semiconductor chip is mounted over the chip mounting part in a direction in which its third principal plane faces the first semiconductor chip. The element mounting part has a notch part. A part of the second semiconductor chip overlaps the notch part. In a region of the third principal plane of the second semiconductor chip that overlaps the notch part, a second electrode pad is provided.
    Type: Application
    Filed: September 16, 2014
    Publication date: March 26, 2015
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi UCHIDA, Kenji NISHIKAWA, Masato KANNO, Mika YONEZAWA, Shunichi KAERIYAMA, Toshinori KIYOHARA