Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract: As a reset transistor is turned on, an FD (Floating Diffusion) is reset to VDD and then stores charges transferred from a light receiving element. By a source-follower circuit formed by an amplifying transistor, a selection transistor and a current source, a voltage in accordance with a potential of FD is output to a data line. A second output circuit generates an output voltage VOUT in accordance with the potential of FD at an output node. Output transistors in output circuit are configured to generate a potential difference equivalent to the potential difference between FD and data line caused by the amplifying transistor and selection transistor, between data line and output node.

Abstract: When at user equipment UE transitions between radio access technology cells, at the transition a timer for controlling when the UE is to send a periodic location registration is reset. This avoids the UE being implicitly detached when it is unable/blocked in the packet-switched PS domain from performing a RAU but would be able to perform a LU, particularly when the UE is in PS/CS modes 1 or 2. Five different embodiments are detailed: the LU timer T3212 is reset with a value of time remaining in a tracking area update TAU timer T3412; T3212 is reset with an initial value for T3212; the RAU timer T3312 is reset with a value of time remaining in the TAU timer T3412; and the T3212 or T3312 reset is conditional on a value of time remaining in a PS backoff timer T3346 exceeding the value of time remaining in the TAU T3412.

Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).

Abstract: In the manufacturing steps of a super-junction power MOSFET having a drift region having a super junction structure, after the super junction structure is formed, introduction of a body region and the like and heat treatment related thereto are typically performed. However, in the process thereof, a dopant in each of P-type column regions and the like included in the super junction structure is diffused to result in a scattered dopant profile. This causes problems such as degradation of a breakdown voltage when a reverse bias voltage is applied between a drain and a source and an increase in ON resistance. According to the present invention, in a method of manufacturing a silicon-based vertical planar power MOSFET, a body region forming a channel region is formed by selective epitaxial growth.

Abstract: There is provided a solid-state image sensing device that can prevent the occurrence of vertical line noise with simple circuit. A timing adjustment circuit generates a first clock supplied to a ramp generator and a second clock supplied to a counter so that a phase difference between the first clock and the second clock is within a predetermined range and differs according to lines in an image sensor.

Abstract: A method, apparatus and computer program product are provided in order to provide for periodic measurements related to a frequency identified by the network, such as a downlink frequency associated with a secondary uplink frequency. In the context of a method, a message is caused to be transmitted to a mobile terminal indicating that the mobile terminal is to perform periodic measurements in relation to a secondary uplink frequency. Following the performance of the periodic measurements by the mobile terminal, the method also includes receiving an indication of the periodic measurements in relation to the secondary uplink frequency that have been performed by the mobile terminal.

Abstract: Embodiments of the present disclosure solve problems of throughput reduction due to collisions, busy medium, and deferred transmission due to overlapping wireless networks (e.g. 802.11 OBSS) by allowing devices suffering from overlapping interference to have sufficient chances to transmit and/or receive successfully. Embodiments include methods for a first device (e.g. 802.11 AP) to communicate data via a medium shared with other devices (e.g. 802.11 APs and/or STAs) located in an overlapping service area but not under common control with the first device. Embodiments also include methods for a first device (e.g. 802.11 AP) to negotiate reservation of a shared medium requested by a second device (e.g. 802.11 AP), the two devices being in overlapping service areas but not under common control. Embodiments include wireless communication devices (e.g. 802.11 APs) and computer programs or computer-readable media embodying one or more of the methods.

Abstract: The semiconductor device includes a tab including a chip supporting surface, and a back surface opposite to the chip supporting surface; a plurality of suspension leads supporting the tab; a plurality of leads arranged between the suspension leads; a semiconductor chip mounted on the chip supporting surface of the tab, the semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a rear surface opposite to the main surface; a seal portion sealing the semiconductor chip such that a part of each of the leads is exposed from the seal portion; and a Pb-free solder formed on the part of each of the leads. A part of the rear surface of the semiconductor chip is contacted with the seal portion.

Abstract: A semiconductor device includes a source electrode pad formed to a front surface of a semiconductor chip and a metal clip (metal plate) to which a lead is electrically connected. The metal clip includes a chip-connecting portion electrically connected to the source electrode pad via a conductive bonding material, a lead-connecting portion electrically connected to the lead via a conductive bonding material, and an intermediate portion positioned between the chip-connecting portion and the lead-connecting portion. Further, between the intermediate portion and the chip-connecting portion, a step portion, which has shear surfaces disposed to face each other, is provided interposing a joining portion.

Abstract: A semiconductor package has a semiconductor chip, a lead frame in which a semiconductor chip is mounted on a die pad, and a resin sealing the semiconductor chip and the die pad from an upper surface and a lower surface, the resin has a concave portion disposed at the surface and a concave portion situated inside the concave portion in a plan view.

Abstract: A semiconductor device includes a substrate, a multilayer wiring layer formed over the substrate, an MTJ (Magnetic Tunnel Junction) element formed in an insulating layer located lower than an uppermost wiring layer in the multilayer wiring layer, a wiring formed in a wiring layer immediately above the MTJ element and coupled to the MTJ element, and a shield conductor region provided in the wiring or a wiring layer immediately above the wiring, and covering an entirety of the MTJ element in a plan view.

Abstract: In a power feeding region of a memory cell (MC) in which a sidewall-shaped memory gate electrode (MG) of a memory nMIS (Qnm) is provided by self alignment on a side surface of a selection gate electrode (CG) of a selection nMIS (Qnc) via an insulating film, a plug (PM) which supplies a voltage to the memory gate electrode (MG) is embedded in a contact hole (CM) formed in an interlayer insulating film (9) formed on the memory gate electrode (MG) and is electrically connected to the memory gate electrode (MG). Since a cap insulating film (CAP) is formed on an upper surface of the selection gate electrode (CG), the electrical conduction between the plug (PM) and the selection gate electrode (CG) can be prevented.

Abstract: In AD conversion of a voltage, data continuity is ensured between the results of conversion after amplification and of direct conversion without amplification. In AD conversion operation, an analog signal output from a DA converter circuit is directly converted by an AD converter circuit, and the analog signal is converted after amplification with an expected gain of 2?. Based on resultant data, a gain of an amplifier circuit and an offset thereof are calculated. An analog signal to be enhanced in bit precision is amplified by the amplifier circuit and converted by the AD converter circuit, the offset is subtracted from the resultant conversion, and the result is multiplied by a ratio of the expected gain to the calculated gain to cancel gain error. Based on data with gain error canceled, acquisition of bit-extended conversion result data is performed to ensure continuity between data having different degrees of bit precision.

Abstract: Disclosed is a high-frequency signal processing device capable of reducing transmission power variation and harmonic distortion. For example, the high-frequency signal processing device includes a pre-driver circuit, which operates within a saturation region, and a final stage driver circuit, which operates within a linear region and performs a linear amplification operation by using an inductor having a high Q-value. The pre-driver circuit suppresses the amplitude level variation of a signal directly modulated, for instance, by a voltage-controlled oscillator circuit. Harmonic distortion components (2HD and 3HD), which may be generated by the pre-driver circuit, are reduced, for instance, by the inductor of the final stage driver circuit.

Abstract: A semiconductor device is reduced in size. The semiconductor device includes a die pad, a plurality of leads arranged around the die pad, a memory chip and a power source IC chip mounted over the die pad, a logic chip mounted over the memory chip, a plurality of down bonding wires for connecting the semiconductor chip to the die pad, a plurality of lead wires for connecting the semiconductor chip to leads, and a plurality of inter-chip wires. Further, the logic chip is arranged at the central part of the die pad in a plan view, and the power source IC chip is arranged in a corner part region of the die pad in the plan view. This reduces the size of the QFN.

Abstract: To provide a semiconductor device provided with a power-on reset circuit that can reliably detect decrease in power-supply voltage. The power-on reset circuit provided on the semiconductor device includes: a first comparison circuit that compares a primary voltage with a reference value; and a second comparison circuit that compares a secondary voltage with the reference value. The power-on reset circuit issues a reset signal based on comparison results of the first and second comparison circuits.

Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

Abstract: The semiconductor integrated circuit device includes a T-type switch circuit TS[k] that is between an input port A[k] and an input terminal Ain of an analog/digital conversion circuit and that includes first, second, and third PMOS transistors MP1, MP2, and MPc, and first, second, and third NMOS transistors MN1, MN2, and MNc; and a fourth PMOS transistor MPu for pre-charging the input terminal Ain to a power supply voltage VCCA. In detecting the presence or absence of a disconnection from the input port A[k] to a signal input terminal Vint[k], first, the input terminal Ain is pre-charged to the power supply voltage VCCA via the fourth PMOS transistor MPu and also the second NMOS transistor MN2 and the second PMOS transistor MP2 are turned on, and the first NMOS transistor MN1, the first PMOS transistor MP1, the third PMOS transistor MPc, and third the NMOS transistor MNc are turned off.