Patents Assigned to RENESAS
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Publication number: 20130285055Abstract: A semiconductor device according to the present invention includes: a through via formed to penetrate a semiconductor substrate; first and second buffer circuits; a wiring forming layer formed in an upper layer of the semiconductor substrate; a connecting wiring portion formed in an upper portion of the through via assuming that a direction from the semiconductor substrate to the wiring forming layer is an upward direction, the connecting wiring portion being formed on a chip inner end face that faces the upper portion of the semiconductor substrate at an end face of the through via; a first path connecting the first buffer circuit and the through via; and a second path connecting the second buffer circuit and the through via. The first path and the second path are electrically connected through the connecting wiring portion.Type: ApplicationFiled: April 5, 2013Publication date: October 31, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Koji TAKAYANAGI
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Publication number: 20130285465Abstract: A transmitter circuit has transistors each of which is provided between an other end of a primary coil to whose one end a power supply voltage is supplied and either of a power supply voltage terminal and a ground voltage terminal, respectively, and a control circuit for, when causing no current to flow through the primary coil, turning on the one transistor and turning off the other transistor.Type: ApplicationFiled: April 19, 2013Publication date: October 31, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Koichi TAKEDA, Shunichi KAERIYAMA
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Publication number: 20130284888Abstract: There is a need to provide a solid-state imaging apparatus capable of highly accurately analog-to-digital converting an analog voltage output from a pixel circuit. The solid-state imaging apparatus supplies a counter code to an integral A/D converter. The counter code CD includes 3-phase clock signals and gray signals. The clock signals each have a cycle equal to specified cycle multiplied by 8 and allow phases to shift from each other by specified cycle. The gray signals linearly increase count values at a cycle equal to specified cycle multiplied by 4. The counter code reverses only the logical level of a signal when a count value changes. A count value error can be limited to a minimum.Type: ApplicationFiled: April 25, 2013Publication date: October 31, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Shunsuke OKURA, Koji SHIDA, Hiroshi KATO
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SEMICONDUCTOR DEVICE INCLUDING WORK FUNCTION ADJUSTING ELEMENT, AND METHOD OF MANUFACTURING THE SAME
Publication number: 20130280872Abstract: A semiconductor device has a substrate; and an N-channel MIS transistor and a P-channel MIS transistor provided on the same substrate; each of the N-channel MIS transistor and the P-channel MIS transistor having a Hf-containing, high-k gate insulating film, and a gate electrode provided over the high-k gate insulating film, the N-channel MIS transistor having a silicon oxide film or a silicon oxynitride film, which contains a first work function adjusting element, provided between the substrate and the high-k gate insulating film, and, the P-channel MIS transistor having a silicon oxide film or a silicon oxynitride film, which contains the first work function adjusting element same as that contained in the N-channel MIS transistor, provided between the high-k gate insulating film and the gate electrode.Type: ApplicationFiled: June 11, 2013Publication date: October 24, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Kenzo MANABE -
Publication number: 20130283016Abstract: Provided is a signal processing circuit occupying a small circuit area. A common arithmetic operation element is shared between a plurality of arithmetic operation sequence control units. An arbitration circuit selects, when the plurality of arithmetic operation sequence control units simultaneously generate requests for arithmetic operations to use the common arithmetic operation element, the predetermined sequence control unit based on priority information about the plurality of arithmetic operation sequence control units, causes the common arithmetic operation element to execute the arithmetic operation requested from the selected arithmetic operation sequence control unit, and returns the result of the arithmetic operation to the selected arithmetic operation sequence control unit.Type: ApplicationFiled: April 17, 2013Publication date: October 24, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hiroyuki YAMASAKI, Hideyuki NODA, Kan MURATA
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Publication number: 20130277842Abstract: A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap.Type: ApplicationFiled: April 20, 2012Publication date: October 24, 2013Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC., RENESAS ELECTRONICS CORPORATION, STMICROELECTRONICS, INC.Inventors: Frieder Hainrich Baumann, Chao-Kun Hu, Andrew H. Simon, Tibor Bolom, Koichi Motoyama, Chengyu Charles Niu
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Publication number: 20130273924Abstract: A wireless device transmits a device-to-device discovery signal using the same transmission resource that is used for transmitting uplink retransmissions to a base station by a second wireless device. The device-to-device discovery signal is transmitted at a power that is determined in accordance with a control signal received by the wireless device from the base station. In an example, the wireless device transmits the device-to-device discovery signal on an uplink control channel established for use for sending uplink control signals to the base station.Type: ApplicationFiled: April 10, 2013Publication date: October 17, 2013Applicant: RENESAS MOBILE CORPORATIONInventors: Sami-Jukka HAKOLA, Matti PIKKARAINEN, Ville VARTIAINEN, Anna PANTELIDOU, Juha Pekka KARJALAINEN, Timo Kalevi KOSKELA, Samuli TURTINEN
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Publication number: 20130272226Abstract: Systems and techniques for managing channel reservation in a full-duplex wireless network. A transmitting node sends a media access control frame to a receiving node, including an integrity check field in a header of the frame. Upon performing an integrity check and determining that the media access control frame is addressed to itself, the receiving node sends a transmission so as to reserve the channel. If the receiving node has no data to send, the transmission may be an acknowledgement field, and if the receiving node has data to send, the transmission may he a media access control frame including an integrity check field in a header of the frame.Type: ApplicationFiled: April 12, 2013Publication date: October 17, 2013Applicant: RENESAS MOBILE CORPORATIONInventor: Wei LI
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Publication number: 20130275929Abstract: In an LSI designing support device and method, in which in an LSI circuit is designed including a logic gate and an FET, a possibility that a steady-state flow-through current from a power source to a ground is generated is determined. In an inputted netlist including a logic gate and an FET, extraction is made of a flow-through condition function which expresses, in terms of a Boolean expression, on/off of an FET arranged in a path from a power source to a ground or a path from the output of a logic gate to the power source or to the ground. A flow-through condition determining Boolean expression of a logic circuit which supplies an input to the flow-through condition function is extracted. The Boolean expression is degenerated with logic equivalence maintained, and the existence or nonexistence of a possibility of satisfying a flow-through condition is determined.Type: ApplicationFiled: March 20, 2013Publication date: October 17, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Keiichi SUZUKI
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Publication number: 20130264637Abstract: Trenches are formed in a base layer and extend parallel to each other. A gate insulating film is formed on the inner wall of each of multiple trenches. A gate electrode GE is buried in each of the trenches. The source layer is formed in the base layer to a depth less than the base layer. The source layer is disposed between each of the trenches. A second conduction type high concentration layer is formed between the source layer and the trench in a plan view. The trench, the source layer, and the second conduction type high concentration are arranged in this order repetitively in a plan view. One lateral side of the trench faces the source layer and the other lateral side of the trench faces the second conduction type high concentration layer.Type: ApplicationFiled: March 27, 2013Publication date: October 10, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hiroaki KATOU, Hiroyoshi KUDOU, Taro MORIYA, Satoshi UCHIYA
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Publication number: 20130266040Abstract: An apparatus, in one embodiment, can include a configuration including a plurality of heat generation devices. The apparatus also includes a plurality of thermal sensors respectively, operably connected to each of the plurality of heat generation devices, wherein each thermal sensor of the plurality of thermal sensors includes a respective output terminal configured to provide a voltage representative of the temperature of the respective heat generation device. The apparatus further includes an output circuit configured to output the highest temperature information among the heat generation devices. The output terminals of the plurality of thermal sensors are tied together. A corresponding method is also discussed.Type: ApplicationFiled: January 25, 2013Publication date: October 10, 2013Applicant: RENESAS ELECTRONICS AMERICA INC.Inventors: Tetsuo Sato, Ryotaro Kudo
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Publication number: 20130259144Abstract: A receiver includes a positive pulse determination circuit and a negative pulse determination circuit. The positive pulse determination circuit outputs a first L-level between when a pulse signal having a negative amplitude is detected and when neither a pulse signal having a positive amplitude nor a pulse signal having a negative amplitude is detected; otherwise a first H-level if a pulse signal having a positive amplitude is detected during another period. The negative pulse determination circuit outputs a second L-level between when a pulse signal having a positive amplitude is detected and when neither a pulse signal having a positive amplitude nor a pulse signal having a negative amplitude is detected; otherwise a second H-level is output if a pulse signal having a negative amplitude is detected during the other period.Type: ApplicationFiled: March 4, 2013Publication date: October 3, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Koichi TAKEDA, Shunichi KAERIYAMA
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Publication number: 20130260294Abstract: A method of manufacturing a semiconductor device in which the alignment accuracy of an immersion exposure device is maintained even when exposure steps are carried out intermittently. In the method, a substrate is placed on a stage of an exposure device (substrate placing step). Then, a first liquid is supplied to between the substrate and the optics system of the exposure device to expose the substrate through the first liquid (exposure step). A second liquid is supplied from a different place from the first liquid to a drainage groove provided around the stage at least in a period other than when the first liquid is supplied onto the stage, in order to suppress change in the temperature of the exposure device.Type: ApplicationFiled: March 2, 2013Publication date: October 3, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Kazuyuki Yoshimochi
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Publication number: 20130256791Abstract: To satisfy both suppression of rise in contact resistance and improvement of breakdown voltage near the end part of a trench part. The trench part GT is provided between a source offset region and a drain offset region at least in plan view in a semiconductor layer, and is provided in a source-drain direction from the source offset region toward the drain offset region in plan view. A gate insulating film GI covers the side surface and the bottom surface of the trench part GT. A gate electrode is provided in the trench part at least in plan view, and contacts the gate insulating film GI. A contact GC contacts the gate electrode GE. The contact GC is disposed, shifted in a first direction perpendicular to the source-drain direction relative to the centerline in the trench part GT extending in the source-drain direction in plan view, and is provided in the trench part GT in plan view.Type: ApplicationFiled: March 3, 2013Publication date: October 3, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Souichirou Iguchi
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Publication number: 20130257379Abstract: A semiconductor device for battery control includes a CPU, a first bus coupled to the CPU, a second bus not coupled to the CPU, and a protective function circuit for protecting a battery from stress applied thereto. The semiconductor device also includes a non-volatile memory storing trimming data, a trimming circuit to perform trimming required to allow the protective function circuit to exert a protective function, and a bus control circuit capable of selectively coupling the first bus and the second bus to the non-volatile memory. The semiconductor device further includes a transfer logic circuit which causes, by making the bus control circuit select the second bus, a trimming data transfer path leading from the non-volatile memory to the trimming circuit to be formed and the trimming data stored in the non-volatile memory to be transferred to the trimming circuit without involving the CPU.Type: ApplicationFiled: March 2, 2013Publication date: October 3, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Daisuke Kato, Ryosuke Enomoto
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Publication number: 20130256792Abstract: The present invention provides a semiconductor device designed to prevent an electric field from being concentrated in the vicinity of a groove portion. The semiconductor includes a semiconductor layer, a source region, a drain region, a source offset region, a drain offset region, a groove portion, a gate insulating film, a gate electrode, and an embedded region. The groove portion is provided in at least a position between the source offset region and the drain offset region in the semiconductor layer in a plan view, in a direction from the source offset region to the drain offset region in a plan view. The gate insulating film covers a side and a bottom of the groove portion. The gate electrode is provided only within the groove portion in a plan view, and contacts the gate insulating film.Type: ApplicationFiled: February 12, 2013Publication date: October 3, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Hiroki MATSUMOTO
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Publication number: 20130256783Abstract: A trench gate type MISFET and a diode are formed in a semiconductor substrate. First and second trenches are formed in the semiconductor substrate. A gate electrode is formed in the first trench through a gate insulating film. A dummy gate electrode is formed in the second trench through a dummy gate insulating film. A cathode n+-type semiconductor region and an anode p-type semiconductor region are formed in the semiconductor substrate and the second trench is formed so as to surround the n+-type semiconductor region in a planar view. A part of the anode p-type semiconductor region is formed directly below the n+-type semiconductor region, so that a PN junction is formed between the part of the anode p-type semiconductor region and the n+-type semiconductor region. Thereby a diode is formed. The dummy gate electrode is electrically coupled to one of an anode and a cathode.Type: ApplicationFiled: February 13, 2013Publication date: October 3, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hiroaki KATOU, Taro MORIYA, Hiroyoshi KUDOU, Satoshi UCHIYA
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Publication number: 20130258739Abstract: A content addressable memory chip which can perform a high speed search with less error is provided. A match amplifier zone determines coincidence or non-coincidence of search data with data stored in the content addressable memory cells in an entry of a CAM cell array, according to the voltage of a match line. The match amplifier zone comprises one or more NMOS transistors and one or more PMOS transistors. The match amplifier zone has a dead zone to an input of a voltage of the match line, and has a property that no flow-through current is present in the match amplifier zone.Type: ApplicationFiled: March 15, 2013Publication date: October 3, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Masanobu KISHIDA
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Publication number: 20130257547Abstract: A conventional semiconductor device has a problem that acquisition of variation information of circuit elements constructing the semiconductor device is not easy. According to an embodiment, a semiconductor device has a control circuit which makes an oscillation circuit operate by at least two operation current values, obtains first frequency information related to frequency of an output signal corresponding to a first operation current value and second frequency information related to frequency of an output signal corresponding to a second operation current value, and obtains manufacture variation information of a circuit element on the basis of the difference between the first and second frequency information.Type: ApplicationFiled: March 3, 2013Publication date: October 3, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Chihiro Arai, Toshiya Uozumi, Keisuke Ueda
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Publication number: 20130256508Abstract: A photoelectric conversion device is provided that has high linearity of output current to illuminance and is applicable to illumination sensors. The photoelectric conversion device outputs appropriate current by complementing first current, which is generated in response to incident light, with complementary current. The complementary current is generated based on second current flowing in response to the light. The second current is generated by a device having the same element area as that of a device that generates the first current. When the second current flows, the complementary current is generated based on a direction of the second current and is then added to the first current.Type: ApplicationFiled: January 28, 2013Publication date: October 3, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Tadashi JAHANA, Hiroyuki Sawano, Seiji Kawata, Masahiro Fujii, Junichi Nakamura
