Abstract: A reduction is achieved in the primary-side input impedance of a transformer (voltage transformer) as an output matching circuit without involving a reduction in Q-factor. An RF power amplifier includes transistors, and a transformer as the output matching circuit. The transformer has a primary coil and a secondary coil which are magnetically coupled to each other. To the input terminals of the transistors, respective input signals are supplied. The primary coil is coupled to each of the output terminals of the transistors. From the secondary coil, an output signal is generated. The primary coil includes a first coil and a second coil which are coupled in parallel between the respective output terminals of the transistors, and each magnetically coupled to the secondary coil. By the parallel coupling of the first and second coils of the primary coil, the input impedance of the primary coil is reduced.

Abstract: A communication device with digital and analog circuits mixedly mounted thereon, for which the influence of noise generated in its interface part on the analog circuit part can be reduced, which does not interfere with the downsizing of the communication device. The communication device has a communication part, such as semiconductor communication device, and a control part, such as a semiconductor control device operable to control the communication part. The communication part and control part are operated in asynchronization with each other. The communication part includes an analog circuit. The interface circuit of the communication part, which is interfaced with the control part, receives a clock signal supplied from the communication part and conducts a synchronous interface. The control part stops supplying the clock signal during the time when the communication part operates the analog circuit.

Abstract: Provided is a multiplexing control unit operable to execute multiplex (MUX) and demultiplex (DEMUX), and enhanced in its processing performance. The multiplexing control unit includes a transport stream (TS) buffer, a multiplex-processing part, a video buffer and an audio buffer. When supplied with coded video and audio data from video and audio buffers, the multiplex-processing part conducts MUX, and on the other executes DEMUX on TS data stored in the TS buffer thereby to produce coded video and audio data. MUX and DEMUX processes by the multiplex-processing part are executed in sets of more than one frame processed according to moving-picture compression coding. Before start of execution of the process, whether or not the requirement of preparation for the execution is satisfied is judged inside the device, in which the judgment is made by checking storing states of the buffers.

Abstract: In an exposure step, a combination of a first photomask and a second mask is used. The first mask has a real pattern corresponding to the pattern actually formed on the film to be processed, and a dummy pattern added for controlling pattern pitch in the first photomask within a prescribed range; and the second photomask has a pattern isolating a real-pattern-formed region from a dummy-pattern-formed region. In forming the pattern, after forming a film to be processed on a substrate, a first mask is formed on the film to be processed, by lithography, using the first photomask, and a second mask is formed on the film to be processed, by lithography, using the second photomask. Thereafter, the film to be processed is etched and removed using the first and second masks as masks to form the pattern.

Abstract: An electronic component for high frequency power amplification realizes an improvement in switching spectrum characteristics. The gain of an amplifying NMOS transistor is controlled by a bias voltage on which a bias control voltage is reflected. Further, a threshold voltage compensator compensates for a variation in threshold voltage with variations in the manufacture of the amplifying NMOS transistor. The threshold voltage compensator includes an NMOS transistor formed in the same process specification as the amplifying NMOS transistor and converts a variation in current flowing through the NMOS transistor depending on the variation in the threshold voltage of the amplifying NMOS transistor to its corresponding voltage by a resistor to compensate for the bias voltage. It is thus possible to reduce variations in so-called precharge level brought to fixed output power in a region (0 dBm or less, for example) low in output power.

Abstract: There is provided a technique for reducing the occurrence of higher harmonics which occur from a field effect transistor, particularly a field effect transistor configuring a switching element of an antenna switch. In a transistor having a meander structure, the gate width of a partial transistor closest to a gate input side is increased. More specifically, a comb-like electrode is made longer than the other comb-like electrodes. In other words, a finger length is made greater than any other finger length. In particular, the comb-like electrode has the greatest length in all the comb-like electrodes.

Abstract: A PFC counter which controls a switching element of voltage step-up chopper circuits arranged in parallel has a circuit (SLOG) generating a switch signal (GD_S) whose phase is shifted from that of a switch signal of one of the switching elements. This circuit has a first counter (COUNTM) which counts clock signals by a cycle unit of one of the switch signals; a second counter (COUNTS) which counts clock signals by a cycle unit having a predetermined phase difference with respect to one of the switch signals; and a first register (REG1) which holds a value counted by the first counter corresponding to a high-level period of one of the switch signals.

Abstract: An improvement is achieved in the mounting reliability of a semiconductor device. A semiconductor chip is mounted over an upper surface of a wiring substrate. A plurality of solder balls are disposed individually over a plurality of lands formed on a lower surface of the wiring substrate. The plural lands include a first land group arranged in a plurality of rows and arranged along a peripheral edge portion of the lower surface of the wiring substrate, and a second land group arranged inside the first land group in the lower surface of the wiring substrate. The lands in the first land group are arranged with a first pitch, and the lands in the second land group are arranged with a second pitch higher than the first pitch.

Abstract: A tuner receives broadcast data on specified channels. A channel search unit controls the tuner to search for available channels, and creates a channel map representing the available channels and a selection order thereof. A channel order setting unit changes setting about enabling/disabling of the selection and/or the selection order of the channels in the channel map. An operation input unit accepts a channel selecting operation of a user. When the user performs an operation for channel forward selection or channel reverse selection through the operation input unit, a channel switching unit changes the selection of the channel according to the channel map and causes the tuner to receive the broadcast data on the selected channel.

Abstract: An RF amplification device has amplification elements which amplify a radio frequency input signal in wireless radio communication. Transmission line transformers are coupled to one of an input electrode and an output electrode of the amplification elements and have a main line Lout arranged between the input and the output, and a sub line Lin1 arranged between an AC ground point and one of the input and the output and coupled to the main line Lout. By applying an operating voltage different from the ground voltage level to the AC ground point, the operating voltage is supplied to the output electrodes of the amplification elements via the sub line from the AC ground point. In realizing a high-performance load circuit in an RF amplification device, it is possible to avoid increase of a module height of an RF module.

Abstract: The present invention provides a reference power supply circuit which does not require trimming and prevents occurrence of deadlock of a band gap reference circuit. An RFID tag chip related to the present invention has a reference power supply including a switch for switching between a band gap reference circuit and a Vth difference reference circuit. A reference potential in band gap reference of the band gap reference circuit and an output of the Vth difference reference circuit are compared by a comparator, and a transistor operating as a switch is controlled, thereby making the reference potential in band gap reference rise, hastening startup of the band gap reference circuit, and preventing occurrence of deadlock in the band gap reference circuit.

Abstract: The present inventors have found that a wafer process of VLSI (Very Large Scale Integration) has the following problem, that is, generation of foreign matters due to moisture from a wafer as a result of degassing when a barrier metal film or a first-level metal interconnect layer is formed by sputtering as a preliminary step for the formation of a tungsten plug in a pre-metal step. To overcome the problem, the present invention provides a manufacturing method of a semiconductor integrated circuit device including, in a plasma process, in-situ monitoring of moisture in a processing chamber by receiving an electromagnetic wave generated from plasma.

Abstract: A memory cell capacitor (C3) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M3) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs.

Abstract: A display drive circuit of the invention has: an initial-color-gamut-apex-coordinate-storing unit capable of storing initial color gamut apex coordinates; a user-target-color-gamut-apex-coordinate-storing unit capable of storing user target color gamut apex coordinates; a saturation-expansion-coefficient-deciding unit for deciding expansion coefficients of saturation data based on the initial and user target color gamut apex coordinates; and an expansion unit for expanding saturations of display data based on the saturation expansion coefficients. The expansion coefficients of saturation data are decided based on the initial and user target color gamut apex coordinates, and saturations of display data are expanded according to the expansion coefficients. Thus, the degree of expanding the saturations can be controlled for each color gamut or each of R, G and B color properties of an LC display panel.

Abstract: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information.

Abstract: A semiconductor device includes a semiconductor layer formed on an insulating layer; a gate electrode disposed on said semiconductor layer via a gate insulating film; a source/drain layer composed by including an alloy layer or a metal layer with a bottom surface in contact with the insulating layer, with joint surfaces to a channel region disposed along crystal orientation faces of said semiconductor layer; and impurity-doped layers formed in a self-aligned manner along interfaces of the alloy layer or the metal layer, and said semiconductor layer.

Abstract: Connector terminals are arranged at the center of a thin memory card 1802, thereby preventing an electrical short circuit between the terminals. A step is provided to the thin memory card 1802, thereby allowing the IC chips to be stacked in a thick portion. Adhesion portions of the connector terminals 3303 are located at a position on a card insertion port side of a substrate 3002, thereby preventing the destruction of the connector terminals at the time of the card insertion. An upper retainer lid 3003 is provided on an upper portion of the connector terminals 3303, thereby preventing the deflection of the card.

Abstract: To provide a technique of supplying a voltage generated in any of a plurality of semiconductor chips to the other chip as a power supply voltage to realize a stable operation of a semiconductor device in which the semiconductor chips are stacked in the same package. In an example of the main technique, two chips are stacked with each other, first to third pads are disposed along corresponding sides of the respective chips, which are arranged close and in parallel to each other, and these pads are commonly connected to each other with first to third metal wires, respectively. In another example, fourth and fifth pads are disposed along a side different from a side along which the first to third pads are disposed, and further connected to each other with a fourth metal wire directly between the chips.

Abstract: One high-frequency switch Qm supplied with transmit and receive signals to ON, and another high-frequency switch Qn supplied with a signal of another system to OFF are controlled. In the other high-frequency switch Qn, to set V-I characteristics of near-I/O gate resistances Rg1n-Rg3n of a near-I/O FET Qn1 near to a common input/output terminal I/O connected with an antenna are set to be higher in linearity than V-I characteristics of middle-portion gate resistances Rg3n and Rg4n of middle-portion FETs Qn3 and Qn4. Thus, even in case that an uneven RF leak signal is supplied to near-I/O gate resistances Rg1n-Rg3n, and middle-portion gate resistances Rg3n and Rg4n, the distortion of current flowing through the near-I/O gate resistances Rg1n-Rg3n near to the input/output terminal I/O can be reduced.

Abstract: A position sensorless drive method capable of driving a permanent magnet motor by an ideal sine-wave current and enabling the driving from an extremely low-speed range in the vicinity of zero-speed is provided. A neutral-point potential of the permanent magnet motor is detected in synchronization with a PWM waveform of an inverter. The position of a rotor of the permanent magnet motor is estimated from the variation of the neutral-point potential. Since the neutral-point potential is varied in accordance with the magnetic circuit characteristics of an individual permanent magnet motor, the position can be detected regardless of the presence of saliency of the permanent magnet motor.