Abstract: The present invention provides a vehicle communication system by which even when the number of other vehicles around a traffic line is increased, it is possible to prevent occurrence of a situation that there are located vehicles the number of which is larger than the capacity of a communicable network, and it is possible to secure communications with the other vehicles. Even when it is determined that a host vehicle enters in a traffic line and a plurality of other vehicles the number of which is larger than a threshold value are located in front and rear virtual regions of the host vehicle, a transmission power is reduced to the extent that communications between the host vehicle and one of the other vehicles that is located furthest in the virtual regions can be secured.

Abstract: A wireless communication system includes: a filter; and a semiconductor chip including a signal processing integrated circuit having an amplifier, wherein a main surface of the semiconductor chip is provided with a plurality of electrode terminals along an edge portion thereof; wherein the amplifier has a transistor including a control electrode, a first electrode through which a signal is outputted, and a second electrode to which a voltage is applied; wherein the control electrode, the first electrode and the second electrode of the transistor are connected to the electrode terminals, respectively; and wherein none of wirings are arranged between the electrode terminals and placements of the control electrode, the first electrode and the second electrode, making space between the electrodes and the electrode terminals narrow.

Abstract: A semiconductor test apparatus, semiconductor device, and test method are provided that enable the realization of a high-speed delay test. Semiconductor test apparatuses (1a-1c) include: flip-flops (11) each provided with first input terminal SI, second input terminal D, mode terminal SE that accepts a mode signal indicating either a first mode or a second mode, clock terminal CK that accepts a clock signal, and output terminal Q, the flip-flops (11) selecting first input terminal SI when the mode signal indicates the first mode, selecting second input terminal D when the mode signal indicates the second mode, and holding information being received by the input terminal that was selected based on the mode signal in synchronization with the clock signal and supplying as output from output terminal Q; and hold unit 12 that holds a set value and that provides the set value to first input terminal SI.

Abstract: A charge pump circuit has boost capacitors and a charge switch supplying supply voltage to the boost capacitors, and a step-up ratio thereof is variable by switching a connection relationship of the boost capacitors. A control circuit unit controls switching of the step-up ratio and selects first operation or second operation depending on a sum-based voltage corresponding to a sum of the supply voltage and a under-charge boost capacitor voltage. The first operation is to turn ON/OFF the charge switch in synchronization with a boost clock signal, while the second operation is to turn OFF it irrespective of the boost clock signal. A value of the sum-based voltage with which the first and second operations are switched is a reference value.

Abstract: A probe is contacted to a test pad, without destroying the circuit formed in the chip at the time of a probe test. Therefore, a load jig, a pressing tool, an elastomer, an adhesion ring, and a plunger are made into one by fixation with a nut and a bolt. The elastic force of the spring installed between the spring retaining jig and the load jig acts so that the member used as these one may be depressed toward pad PD. The thrust transmitted from the spring in a plunger to a thin films sheet is used only for the extension of a thin films sheet.

Abstract: It is desired to make it possible to generate a layout whose chip area is small for a semiconductor integrated circuit having a plurality of power supply systems in an internal circuit region. Power supply line of a first power supply is generated in an internal circuit region. Each of primitive cells is generated so that it is connected to the power supply line. It is checked whether or not the timing of a signal supplied to each of the primitive cells from the power supply line of the first power supply satisfies a prescribed criterion. A line for supplying a second potential generated by a second power supply to replace a first potential generated by the first power supply is generated for at least one power supply separation object cell being at least one of the primitive cells after it is checked that the prescribed criterion is satisfied.

Abstract: To provide a power supply unit capable of realizing a multiphase power supply at low cost. For example, each of a plurality of semiconductor devices DEV[1]-DEV[n] comprises a trigger input terminal TRG_IN, a trigger output terminal TRG_OUT, and a timer circuit TM that delays a pulse signal input from TRG_IN and outputs it to TRG_OUT. DEV[1]-DEV[n] are mutually coupled in a ring shape by its own TRG_IN being coupled to TRG_OUT of one semiconductor device other than itself. Each of DEV[1]-DEV[n] performs switching operation by using the pulse signal from TRG_IN as a starting point, and feeds a current into an inductor L corresponding to itself. Moreover, DEV[1] generates the above-described pulse signal only once during startup by a start trigger terminal ST being set to a ground voltage GND, for example.

Abstract: The present invention makes it possible to obtain: a semiconductor device capable of forming a highly reliable upper wire without a harmful influence on the properties of the magnetic material for an MTJ device; and the manufacturing method thereof. Plasma treatment is applied with reducible NH3 or H2 as pretreatment. Thereafter, a tensile stress silicon nitride film to impose tensile stress on an MTJ device is formed over a clad layer and over an interlayer dielectric film where the clad layer is not formed. Successively, a compressive stress silicon nitride film to impose compressive stress on the MTJ device is formed over the tensile stress silicon nitride film. The conditions for forming the tensile stress silicon nitride film and the compressive stress silicon nitride film are as follows: a parallel plate type plasma CVD apparatus is used; the RF power is set in the range of 0.03 to 0.4 W/cm2; and the film forming temperature is set in the range of 200° C. to 350° C.

Abstract: A semiconductor device having two semiconductor chips sealed in a sealant (2-in-1 package) is provided. A power MOSFET chip for control is disposed on an input-side plate lead portion, wherein a source electrode and a gate electrode are formed on a main surface of the chip and the source electrode is connected to an output plate lead portion. A power MOSFET chip for synchronization is disposed on an output-side plate lead portion, wherein a source electrode and a gate electrode are formed on a main surface of the chip, and the second source electrode is connected to a ground-side plate lead portion. The ground-side plate lead portion and gate-side lead portions connected to the gate electrodes, respectively, are provided between the input-side plate lead portion and the output-side plate lead portion. In this manner, heat-dissipation paths via wirings when the 2-in-1 package is mounted on a board can be wide.

Abstract: A liquid crystal display device comprises a liquid crystal display panel and a semiconductor integrated circuit for driving and controlling the liquid crystal display panel. The number of input/output wires connected to I/O terminals (bonding pads) of the semiconductor integrated circuit is reduced so as to simplify wiring patterns of the I/O wires, whereby degrees of freedom in arranging the I/O wiring patterns are enhanced. The panel has a pair of insulating substrate, and the semiconductor integrated circuit is mounted on one of the paired substrates. The semiconductor integrated circuit has a mode terminal which is fixed to a power supply potential or to a reference potential during operation of the integrated circuit, and power supply dummy terminals connected to the power supply potential or reference potential inside the semiconductor integrated circuit. The wiring patterns formed on the paired insulating substrates connect the mode terminal to the power supply dummy terminals.

Abstract: An input transistor unit includes a first transistor having a control electrode to which a reference voltage is supplied. An output transistor unit includes a diode-connected second transistor. At least one of the input transistor unit and the output transistor unit further includes a third transistor that is diode-connected and connected in series with the corresponding first transistor or the second transistor and outputs a current in the same direction as the corresponding transistor does. The number of transistors included in the input transistor unit and the number of transistors included in output transistor unit are different from each other. The size of transistors included in the input transistor unit differs from that of transistors included in the output transistor unit.

Abstract: In a process for a semiconductor typically represented by a vertical power MOSFET, etc. of repeating various fabrications in a state of a thin film wafer with the thickness of the wafer being 200 ?m or less, it is a standard procedure of conducting processing in a stage of bonding a reinforcing glass sheet to a device surface of the wafer (main surface on the side of surface) in the step after film thickness-reduction. However according to the study of the present inventors, it has been found that about 70% for the manufacturing cost is concerned with the reinforcing glass sheet. In the present invention, a stress relief insulation film pattern is formed to the peripheral end of the rear face of a wafer in which processing to the device surface (surface side face) of the wafer has been completed substantially and back grinding has been applied.

Abstract: A semiconductor device has a sealing body formed of an insulating resin and a semiconductor chip positioned within the sealing body. A gate electrode and a source electrode are on a first main surface of the semiconductor chip and a back electrode (drain electrode) is on a second main surface thereof. An upper surface of a portion of a drain electrode plate that projects in a gull wing shape is exposed from the sealing body and a lower surface thereof is connected to the back electrode through an adhesive. A gate electrode plate projects in a gull wing shape on an opposite end side of the sealing body and is connected to the gate electrode within the sealing body. A source electrode plate projects in a gull wing shape on the opposite end side of the sealing body and is connected to the source electrode within the sealing body.

Abstract: To prevent, in a resin-sealed type semiconductor package, generation of cracks in a die bonding material used for mounting of a semiconductor chip. A semiconductor chip is mounted over the upper surface of a die pad via a die bonding material, followed by sealing with an insulating resin. The top surface of the die pad to be brought into contact with the insulating resin is surface-roughened, while the bottom surface of the die pad and an outer lead portion are not surface-roughened.

Abstract: It has been found by the present inventors, et. al. that, in a modern 0.15 ?m power MOSFET, aluminum voids (voids formed in aluminum type electrode) are generated frequently in trench portions (source contact trenches) caused by the reduction of a cell pitch for refinement. It is considered to be attributable to that the defects are generated mainly due to sudden increase of the aspect ratio from 0.84 in the previous generation to 2.8 in the current generation. That is, according to an invention of the present application, concave portions of repetitive trenches having a high aspect ratio are filled with an aluminum type metal by ionized sputtering through out the processing from the formation to the filling of an aluminum type metal seed film.

Abstract: As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked structure is made to have smaller dielectric constant than that at an upper-layer part thereof, and further this insulation film is a silicon oxide (SiO) film and has, in the interior thereof, nano-pores of from 0.05 nm or more to 4 nm or less in diameter as chief construction. This makes it possible to dramatically reduce effective dielectric constant while keeping the mechanical strength of the conductor layers themselves, and can materialize a highly reliable and high-performance semiconductor device having mitigated the wiring delay of signals which pass through wirings.

Abstract: A semiconductor device has operation modes selectable through the control by a second microcomputer (113). In a first mode, an operation of a memory controller (105) responding to a memory card command from a memory card interface terminal and an operation of a first microcomputer (106) responding to an IC card command from an IC card interface terminal are separately performed. In a second mode, the first microcomputer operates in response to the IC card command from the IC card interface terminal. In a third mode, the memory controller and the first microcomputer operate in response to an undefined IC card command from the IC card interface terminal. In a fourth mode, the memory controller and the first microcomputer operate in response to the memory card command from the memory card interface terminal. Convenience of the semiconductor device having an IC card function and a memory card function is improved.

Abstract: A peripheral circuit with a host load adjusting function which is capable of readily carrying out control so that the amounts of data processed by the peripheral circuit and a host CPU are balanced by limiting interrupts made by the peripheral circuit, usage of a memory bus bandwidth, and a processing throughput of data. A typical embodiment of the present invention has an adjustment limitation setting unit setting a minimum value of an interval of interrupt requests generated by the peripheral circuit with the host load adjusting function, and a cycle counter counting generation timing of the interrupt requests, and compares a value of the cycle counter with the interval set in the adjustment limitation setting unit, thereby suppressing the interrupt requests generated at an interval shorter than the set interval.

Abstract: In a semiconductor device such as a high-frequency power amplifier module, a plurality of amplifying means are formed on a semiconductor chip which is mounted on a main surface of a wiring substrate, and electrodes of the semiconductor chip are electrically connected by wires to electrodes of the wiring substrate. In order to make the high-frequency power amplifier module small in size, a substrate-side bonding electrode electrically connected to a wire set at a fixed reference electric potential is place at a location farther from a side of the semiconductor chip than a substrate-side output electrode electrically connected to an output wire. A substrate-side input electrode electrically connected to an input wire is located at a distance from the side of the semiconductor chip about equal to the distance from the side of the semiconductor chip to the substrate-side output electrode, or at a location farther from the side of the semiconductor chip than the substrate-side bonding electrode is.

Abstract: The present invention provides a technology capable of achieving an improvement in the characteristic of a power amplifier when a power amplifier mounted onto mobile communication equipment such as a cellular phone is comprised of the balance amplifier. One feature of an embodiment resides in that each of passive parts disposed in a low-band signal negative path and each of passive parts disposed in a low-band signal positive path are placed in positions where they are symmetric with respect to a center line of a semiconductor chip. Thus, the symmetry between the low-band signal negative path and the low-band signal positive path is enhanced. As a result, a loss in matching due to the difference between the low-band signal negative path and the low-band signal positive path can be enough reduced, and the characteristic of a low-band signal balance amplifier can be enhanced.