Abstract: A photographing control device capable of storing images to be stored at appropriate timings is provided. The analysis result acquiring unit acquires an analysis result of an image obtained by photographing an object by the photographing device. The status acquisition unit acquires a detection result obtained by detecting the status of the object by the sensor. The index determination unit determines the degree of these indexes for each of a plurality of indexes including those relating to the object based on the image analysis result and the detection result of the state of the object. The evaluation value calculation unit calculates an evaluation value for evaluating the stored value of the image using the degree of the index. When the evaluation value exceeds a predetermined threshold value, the image storage control unit 15 controls so as to store an image.

Abstract: A logic BIST circuits concurrently execute a first scan test for a scan chain as a target and a second scan test for a scan chain as a target, when they are set to a an LBIST mode, and execute the first scan test without executing the second scan test, when they are set to a simultaneous test mode. Memory BIST circuits execute a test for memory circuits concurrently with the first scan test, when they are set to the simultaneous test mode.

Abstract: The reliability of resistive field plate part-containing semiconductor device is improved. In peripheral region of semiconductor chip, the outer circumference end of internal circulation wire is separated from outer circumference end of first conductor pattern of resistive field plate part toward element region. Inner circumference end of external circulation wire is separated from inner circumference end of second conductor pattern of resistive field plate part toward outer circumference of the chip. First conductor pattern of resistive field plate part is partially extended to over thin insulation film to form first lead-out part, and internal circulation wire and first lead-out part of first conductor pattern are electrically coupled via first coupling hole.

Abstract: To allow a metal oxide film composed mainly of O and at least one of Hf and Zr to exhibit ferroelectric properties. After deposition of a hafnium oxide film on a semiconductor substrate via an insulating film, the semiconductor substrate is exposed to microwaves to selectively heat the hafnium oxide film. This makes it possible to form a larger number of orthorhombic crystals in the crystals of the hafnium oxide film. The hafnium oxide film thus obtained can therefore exhibit ferroelectric properties without adding, thereto, an impurity such as Si. This means that the hafnium oxide film having a reverse size effect can be used as a ferroelectric film of a ferroelectric memory cell and contributes to the manufacture of a miniaturized ferroelectric memory cell.

Abstract: A semiconductor die is disclosed upon which is formed direct current (DC) isolated first and second circuits. The first circuit is configured for electrical connection to a first ground. The second circuit is configured for electrical connection to a second ground. The first and second grounds can be at different potentials. The first and second circuits were formed using front end of line (FEOL) and back end of line (BEOL) processes. The first circuit includes a plurality of first devices, such as transistors, which were formed during the FEOL process, and the second circuit includes only second devices, such as transistors, which were formed during the BEOL process.

Abstract: An abnormality detection apparatus includes a feature extraction unit configured to extract an image feature according to a common algorithm, a flow calculation unit, a first abnormality detection unit, and a second abnormality detection unit. An extraction range for the image feature is composed of a predetermined first partial area in a first image, a predetermined second partial area in a second image, and areas near places in the first and second images predicted as destinations of the feature point. The first abnormality detection unit detects an abnormality in the first (second) image based on an optical flow for a feature point in the first (second) partial area. The second abnormality detection unit detects an abnormality by using a feature point in a first overlapped extraction area defined in a first overlapped area and a feature point in a second overlapped extraction area defined in a second overlapped area.

Abstract: An object of the present invention is to provide an information input device capable of realizing high-precision touch operations. The information input device includes a first surface for displaying input request information, a second surface for inputting input request information, a viewpoint calculator for calculating a viewpoint direction of an input person, and a coordinate corrector for correcting a position input to the second surface into a second position in response to the viewpoint direction of the input person and inputs the input request information on the first surface corresponding to the second position. The information input device further provides a storage device for holding distance information on distance between the first surface and the second surface.

Abstract: A simple battery and battery charger. In one embodiment, the battery charger includes an output terminal that provides a charging voltage Vout and charging current Iout. The battery is contained in a battery pack having an input terminal, which can be connected to the output terminal in order to receive Vout and Iout. The battery charger may include a first circuit for controlling the magnitude of Vout. The battery pack may include a second circuit that generates a control signal when the output terminal is connected to the input terminal. The first circuit is configured to control the magnitude of Vout based on the control signal.

Abstract: The present disclosure provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an interlayer insulating film. Vias are formed in each layer on a dicing region side. The vias are formed at the same intervals in a matrix as viewed in a top view. Even in the case where cracking occurs at the time of dicing, the cracking can be prevented from spreading to a seal ring by the vias. As a result, resistance to moisture absorbed in a circuit formation region can be improved, and deterioration in reliability can be prevented.

Abstract: To enhance the performance of a semiconductor device. Gate electrodes extending in a Y direction and applied with a gate potential, and emitter regions and base regions both applied with an emitter potential are formed in an active cell area. The plural emitter regions are formed so as to be separated from each other in the Y direction by the base regions. A plurality of hole discharge cell areas having a ring-shaped gate electrode applied with an emitter potential are formed within an inactive cell area. The hole discharge cell areas are arranged to be separated from each other along the Y direction. Thus, an input capacitance of an IGBT is reduced, and a switching loss at turn on of the IGBT is improved.

Abstract: A display data correction apparatus is provided with: a control circuit responsive to an input gray-level value for initially providing first to N-th control points (N?3) defined in a coordinate system in which a first coordinate axis is associated with the input gray-level value and a second coordinate axis is associated with an output gray-level value to be calculated for the input gray-level value; and a processing circuit obtaining an output gray-level value by repeating an update operation in which the first to N-th control points are updated. The degree (N?1) Bezier curve is used as an approximated curve of the gamma curve. The output gray-level value is finally obtained as the coordinate value of a specific point in the degree (N?1) Bezier curve along the second coordinate axis, where the specific point has the coordinate value closest to the input gray-level value along the first coordinate axis.

Abstract: The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113, and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101. The interconnect component 101 has a constitution where an interconnect layer 103, a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.

Abstract: There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an SRAM memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation. At the same time, the write assist circuit controls the reduction speed of the voltage level of the memory cell power supply line, according to the pulse width of a write assist pulse signal. The pulse width of the write assist pulse signal is defined in such a way that the greater the number of rows (or the longer the length of the memory cell power supply line), the greater the pulse width.

Abstract: The aim of the present disclosure is to provide a watchdog timer that can perform a fault diagnosis during the actual use of a semiconductor device. In a semiconductor device provided with a watchdog timer, the watchdog timer includes a counter; a counter control circuit that changes a count value of the counter to a desired value in the refresh period of the count value; and a fault diagnosis module. The fault diagnosis module includes a suppressing circuit that suppresses generation of a reset signal to the exterior of the watchdog timer in the refresh period; and a holding circuit that holds the reset signal.

Abstract: It is possible to detect a failure in a temperature sensor while preventing enlarging of a circuit scale. A temperature measurement circuit 10 includes temperature sensors 20 and 30, and a comparator 40. The temperature sensor 20 includes a temperature detection unit 21 including a resistive element, a resistance value of which varies in accordance with temperature changes, and an AD converter which converts a voltage of the temperature detection unit 21 into a temperature digital value D1. The temperature sensor 30 includes a ring oscillator 31 which oscillates at a cycle that is temperature dependent, and generates a digital value D2 based on an oscillating signal output by the ring oscillator 31. The comparator 40 compares the temperature digital values D1 and D2, and outputs a signal indicating whether the temperature sensor 20 is normal or not based on a comparison result.

Abstract: The performances of a semiconductor device of a memory element are improved. Over a semiconductor substrate, a gate electrode for memory element is formed via overall insulation film of gate insulation film for memory element. The overall insulation film has first insulation film, second insulation film over first insulation film, third insulation film over second insulation film, fourth insulation film over third insulation film, and fifth insulation film over fourth insulation film. The second insulation film is an insulation film having charge accumulation function. Each band gap of first insulation film and third insulation film is larger than the band gap of second insulation film. The third insulation film is polycrystal film including high dielectric constant material containing metallic element and oxygen. Fifth insulation film is polycrystal film including the same material as that for third insulation film. Fourth insulation film includes different material from that for third insulation film.

Abstract: The present embodiments relate generally to power controllers, and more particularly to synthetic current hysteretic control of a buck-boost DC-DC controller. In one or more embodiments, a controller includes PFM-PWM and Buck-Boost transitions with minimal circuitry and power consumption. In these and other embodiments, a window comparator structure is provided that is capable of generating control signals for use in buck, boost and buck-boost modes of operation.

Abstract: A data transfer apparatus capable of effectively performing image transfer in a simple manner is provided. The data transfer apparatus that transfers image data in an image buffer memory to a display includes: a packet generation section that generates a transfer packet included of valid data and dummy data, the valid data being the image data, and transfers the transfer packet to the display; and a packet generation section that adjusts a ratio between the valid data and the dummy data in the transfer packet based on a data storage amount in the image buffer memory.

Abstract: Related semiconductor devices have a problem in which analysis processing with high defect reproducibility cannot be performed. According to an embodiment, a semiconductor device includes a first arithmetic core that executes a first program stored in a first code area using a first local memory area and a second arithmetic core that executes a second program stored in a second code area using a second local memory area. In an analysis mode, the semiconductor device performs first analysis processing that causes both the first arithmetic core and the second arithmetic core to execute the first program and second analysis processing that causes both the first arithmetic core and the second arithmetic core to execute the second program, and compares a plurality of arithmetic result data pieces acquired from the first and second analysis processing to thereby acquire analysis information used for defect analysis.

Abstract: It is possible to prevent a central processing unit and a security processing unit from accessing of a non-volatile memory at the same time. A data flash 13 includes a secure area 31 and a user area 32. In the secure area 31, a plurality of pieces of security information used in a security process is stored. A security IP 12 reads out a portion of the plurality of pieces of security information from the secure area 31 and stores it in the secure RAM 22. When the security information to be used in the security process is stored in the secure RAM, the security IP 12 reads out the security information from the secure RAM 22 and uses it.