Patents Assigned to RENESAS
  • Driving circuit, semiconductor device including the same, and control method of the driving circuit
    Patent number: 10665271
    Abstract: According to an embodiment, a word line driver includes: a first inverter that is driven by a first power supply voltage and inverts and outputs a decode signal; a second inverter that is driven by a second power supply voltage and inverts and outputs the decode signal; a first PMOS transistor that is controlled to be turned on or off on the basis of an output signal of the second inverter; a first NMOS transistor that is controlled to be turned on or off on the basis of an output signal of the first inverter; and a second PMOS transistor that is provided between a power supply voltage terminal to which the second power supply voltage is supplied and the gate of the first PMOS transistor and is temporarily turned on in synchronization with falling of the decode signal.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: May 26, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koichi Takeda, Takashi Iwase
  • DATA PROCESSING DEVICE
    Publication number: 20200159528
    Abstract: A data processing device has an instruction decoder, a control logic unit, and ALU. The instruction decoder decodes instruction codes of an arithmetic instruction. The control logic unit detects the effective data width of operation data to be processed according to the decode result from the instruction decoder and determines the number of cycles for the instruction execution corresponding to the effective, data width. The ALU executes the instruction with the number of cycles of the instruction execution determined by the control logic unit.
    Type: Application
    Filed: January 21, 2020
    Publication date: May 21, 2020
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Sugako OHTANI, Hiroyuki KONDO
  • Semiconductor storage device including memory cells, word driver, dummy word driver
    Patent number: 10658028
    Abstract: A semiconductor storage device includes a plurality of memory cells arranged in a matrix, a word line provided corresponding to a memory cell row, a dummy word line formed in a metal interconnection layer adjacent to a metal interconnection layer in which the word line is formed, a word driver circuit configured to drive the word line, and a dummy word driver circuit configured to increase voltage on the word line based on interline capacitance between the word line and the dummy word line.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: May 19, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuichiro Ishii, Shinji Tanaka
  • Semiconductor device
    Patent number: 10659016
    Abstract: Provided is a level shifter which can retain an operation margin and enhance an exceeded-breakdown-voltage preventing effect. The level shifter in an embodiment includes an exceeded-breakdown-voltage prevention circuit between a pair of first-conductivity-type cross-coupled transistors and a pair of second-conductivity-type input transistors. The exceeded-breakdown-voltage prevention circuit includes first-conductivity-type first transistors and second-conductivity-type second transistors which are coupled in series to each other, and first-conductivity-type third transistors coupled in series to the first and second transistors on a higher-potential side.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: May 19, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoji Kashihara
  • Video signal receiving apparatus and video signal receiving method
    Patent number: 10659722
    Abstract: A video signal receiving apparatus receives a first and second video signals for transmitting a same video content. When determining a size adjustment amount of a second video included in the second video signal, the video signal receiving apparatus performs scaling processing on a second image included in the second video signal to generate a scaling image and performs shift processing on the second image to generate a shift image. The video signal receiving apparatus calculates a similarity degree between a first image included in the first video signal and the scaling image, calculates a similarity degree between the first image and the shift image, and uses the scaling image or the shift image having the higher calculated similarity degree as an image to be subjected to the next scaling processing and the next shift processing.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: May 19, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuichi Takagi, Ren Imaoka
  • Control system and semiconductor device
    Patent number: 10654427
    Abstract: A semiconductor device for controlling an apparatus includes a first memory that stores data indicating, in association with each other, a factor that occurs with respect to the apparatus and control contents of the apparatus to be performed with respect to the factor; a second memory, and a processor executing program instructions and configured to estimate the factor and a required time until encountering the factor based on a result of an observation of a periphery of the apparatus, and decide control contents of the apparatus based on the estimated factor and the data, to control the apparatus. The first memory stores data which a required time until encountering the factor is greater than a threshold, and the second memory stores data which a required time until encountering the factor is equal to or less than the threshold.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: May 19, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yuki Kajiwara
  • Semiconductor device and method of manufacturing same
    Patent number: 10656442
    Abstract: In an optical waveguide supplied with electricity by using a heater, miniaturization of the device is achieved by enhancing heat dissipation efficiency and heat resistance. In a modulator including an optical waveguide formed on an insulating film, a first interlayer insulating film that covers the optical waveguide, a heater formed on the first interlayer insulating film, and a second interlayer insulating film that covers the heater, a heat conducting portion adjacent to the optical waveguide and the heater and penetrating the first and second interlayer insulating films is formed.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: May 19, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Tetsuya Iida, Yasutaka Nakashiba, Shinichi Kuwabara
  • Semiconductor device
    Patent number: 10659026
    Abstract: A semiconductor device that can perform voltage monitoring with a small circuit area is provided. The resistive subdivision circuit RDIV performs the resistive subdivision of the input voltage Vin by means of the input ladder resistor (R1-R4), and drives the nMOS transistors MN1-MN3 by the subdivided input voltages Vi1-Vi3 each having different resistive subdivision ratios, respectively. The pMOS transistor MP0 is provided in common for the pMOS transistors MP1-MP3, and configures a current mirror circuit with each of the pMOS transistors MP1-MP3. The bias current generating circuit IBSG supplies a bias current to the pMOS transistor MP1.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: May 19, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masataka Minami
  • Transformer less battery charger system
    Patent number: 10658855
    Abstract: A transformer less battery charger system. In one embodiment, the battery charger system includes input terminals for receiving an AC voltage, output terminals for receiving terminals of a rechargeable battery pack, and a non-isolated DC-DC converter coupled between the input terminals and the output terminals. A device is also coupled somewhere between the input terminals and the output terminals. The device is configured to selectively and indirectly couple the input terminals to the output terminals. More particularly, the device indirectly couples the input terminals to the output terminals when the rechargeable battery pack terminals are received by the output terminals, and the device indirectly decouples the input terminals from the output terminals when the rechargeable battery pack terminals are separated from the output terminals.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: May 19, 2020
    Assignee: Renesas Electronics America Inc.
    Inventors: Tetsuo Sato, Shigeru Maeta, Toshio Kimura, Atsushi Mitamura, Akira Negishi, Gary S. Jacobson
  • Semiconductor device including a plurality of nitride semiconductor layers
    Patent number: 10658469
    Abstract: In a semiconductor device (MISFET) having a gate electrode formed over a nitride semiconductor layer with a gate insulating film interposed therebetween, the gate insulating film includes a first gate insulating film (oxide film of first metal) formed on the nitride semiconductor layer and a second gate insulating film (oxide film of second metal). The second metal (for example, Hf) has electronegativity lower than that of the first metal (for example, Al). Since the electronegativity of the second metal is lower than that of the first metal, negative charge is introduced into the oxide film of the first metal due to interfacial polarization, so that the flat-band voltage can be shifted in a positive direction. Accordingly, the threshold voltage which has become negative due to the heat treatment of the oxide film of the first metal can be shifted in the positive direction.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: May 19, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshihiro Iizuka, Shin Koyama, Yoshitake Kato
  • Semiconductor memory device having memory cell pairs defining data based on threshold voltages
    Patent number: 10658031
    Abstract: To provide a semiconductor memory device capable of storing multi-value data while suppressing an increase in the threshold voltage set for a memory cell. A semiconductor memory device according to an embodiment includes a plurality of memory cell pairs, each having a first memory cell and a second memory cell. The first memory cell is configured so as to set at least one threshold voltage, whereas the second memory cell is configured so as to set a plurality of threshold voltages. Data stored in the memory cell pairs is defined using differences between the threshold voltages of the second memory cell and the threshold voltage of the first memory cell.
    Type: Grant
    Filed: August 25, 2018
    Date of Patent: May 19, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Hirokazu Nagase
  • Semiconductor device
    Patent number: 10656201
    Abstract: According to one embodiment, a semiconductor device performs processing based on a user program by using a user program, which is used in a normal mode, as an analysis program and making a plurality of peripheral circuits having the same function operate in lock-step where the plurality of peripheral circuits operate in the identical manner, and makes failure diagnosis of the peripheral circuits by determining match or mismatch of a plurality of analysis information respectively obtained from the plurality of peripheral circuits operating in lock-step.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: May 19, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takuya Lee, Tetsuya Kokubun, Yutaka Nakadai, Kenji Shiozawa, Yoshihide Nakamura
  • Semiconductor device, power module, and control method of power conversion device
    Patent number: 10658947
    Abstract: The junction temperature of a field effect transistor is detected with a higher degree of accuracy than in the past. A semiconductor device controls multiple field effect transistors that configure a power conversion device, and includes a differential amplifier and a controller that controls ON/OFF of the multiple field effect transistors. The differential amplifier detects the potential difference between a source and a drain of a field effect transistor that is controlled in the OFF state by the controller and that induces an electric current flowing through the body diode thereof, among the multiple field effect transistors.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: May 19, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Satoshi Narumi
  • Semiconductor device and method of manufacturing the same
    Patent number: 10651277
    Abstract: In a vertical power MOSFET having a superjunction structure, the withstand voltage of the power MOSFET can be ensured even if the aspect ratios of an n-type column region and a p-type column region are increased so as to vary the impurity concentration of the p-type column region. P-type semiconductor regions PR1 are formed on the sides of an n-type column NC1 adjacent to a p-type column region PC1. In this configuration, the p-type semiconductor region PR1 is formed from the upper end of the n-type column region NC1 to about a half depth of a height from the upper end to the lower end of the side of the n-type column region NC1. This inclines the sides of the overall p-type column region including the p-type semiconductor regions PR1 and the p-type column region PC1.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: May 12, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Yuya Abiko, Natsuo Yamaguchi, Satoshi Eguchi
  • Semiconductor device and method of manufacturing same
    Patent number: 10651094
    Abstract: To provide a semiconductor device having improved reliability. An element isolation region comprised mainly of silicon oxide is buried in a trench formed in a semiconductor substrate. The semiconductor substrate in an active region surrounded by the element isolation region has thereon a gate electrode for MISFET via a gate insulating film. The gate electrode partially extends over the element isolation region and the trench has a nitrided inner surface. Below the gate electrode, fluorine is introduced into the vicinity of a boundary between the element isolation region and a channel region of MISFET.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: May 12, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hideki Aono, Tetsuya Yoshida, Makoto Ogasawara, Shinichi Okamoto
  • Common MCU self-identification information
    Patent number: 10649895
    Abstract: Common microcontroller unit (MCU) self-identification information is disclosed. In one embodiment, an MCU is contained in a package. The MCU includes a central processing unit (CPU) and a non-volatile memory. This non-volatile memory stores information specific to the MCU and/or the package. The non-volatile memory also stores a common main program that, when executed by the CPU, accesses the information. The information enables the common main program to adapt itself to resources of the MCU and/or package that are identified in the information.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: May 12, 2020
    Assignee: Renesas Electronics America Inc.
    Inventors: Jon Matthew Brabender, Bernd Willi Westhoff
  • Semiconductor device
    Patent number: 10650949
    Abstract: A semiconductor device capable of reducing in size thereof and suppressing degradation in the characteristics of circuit components is provided. The semiconductor device includes an LC circuit comprised of a spiral inductor provided over a semiconductor substrate and a capacitive element coupled with the spiral inductor. The spiral inductor includes a central area encircled with a metal wiring and a peripheral area other than the central area. The capacitive element is formed in an upper-layer or a lower-layer position corresponding to the peripheral area other than the central area.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: May 12, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hironori Asano, Noriaki Matsuno
  • Semiconductor device
    Patent number: 10650883
    Abstract: In a semiconductor device, memory modules each having a low power consumption mode that is enabled and disabled by a control signal belong to a memory block. A transmission path of the control signal is provided such that the control signal is inputted in parallel to the memory module via an inside-of-module path, and such that the control signal is outputted by a particular memory module of the memory modules via the inside-of-module path to a downstream outside-of-module path. The particular memory module in the memory block is selected such that it has a greater storage capacity than the other memory modules belonging to this same memory block have.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: May 12, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takashi Yamaki
  • Inspection system, inspection device, and inspection method
    Patent number: 10649830
    Abstract: It is determined whether an arithmetic operation function of a device to be inspected is normal or not. A MCU 13 to be inspected acquires a constant to be used for an arithmetic problem from a power source IC 12 on an inspection side. The MCU 13 sequentially selects a plurality of the arithmetic problems and carries out an arithmetic operation using the acquired constant according to the selected arithmetic problem. A monitoring circuit 23 of the power source IC 12 receives the result of the arithmetic operation of the arithmetic problem from the MCU 13. The monitoring circuit 23 compares the received arithmetic operation result with the arithmetic operation result of the arithmetic problem calculated at the side of the monitoring circuit 23. The monitoring circuit 23 determines whether the arithmetic operation function of the MCU 13 works normally or not based on the comparison result.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: May 12, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Seiichi Kousokabe
  • Semiconductor device and method of manufacturing the same
    Patent number: 10651301
    Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having an upper surface, a trench electrode placed inside a trench formed on the upper surface, and a trench insulating film placed between the trench electrode and the semiconductor substrate, and the semiconductor substrate includes a drift layer, a floating layer for electric field reduction, a hole barrier layer, a body layer and an emitter layer, and the emitter layer, the body layer and the hole barrier layer are separated from the drift layer by the floating layer for electric field reduction, and a path of a carrier passing through an inverted layer formed in the body layer includes the body layer, the hole barrier layer, a non-inverted region of the floating layer for electric field reduction, and the drift layer.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: May 12, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Ryo Kanda, Hitoshi Matsuura