Abstract: A method of determining a position of a focus lens includes the steps of detecting luminance values corresponding to a plurality of imaging elements which detect light via a focus lens while moving the focus lens, calculating a contrast value for evaluation of a focused state of a subject image on the basis of the detected luminance values corresponding to the imaging elements, specifying the largest luminance value in the detected luminance values corresponding to the imaging elements, specifying a range in which the largest luminance value is not less than a value which is determined in advance in a moving range of the focus lens and determining the position of the focus lens on the basis of the contrast value in the specified range of the position of the focus lens.

Abstract: According to one embodiment, a memory controller is configured so that when the memory controller controls a writing/erasing process for a flash memory performed by a first or second master, the memory controller can prohibit, while the first master is performing the writing/erasing process for the flash memory, an interruption of the writing/erasing process in execution, the interruption resulting from access to the flash memory by the second master.

Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.

Abstract: A super scale switched capacitor for an integrated circuit is disclosed. In one embodiment the super scale switched capacitor circuit includes a capacitor coupled between a first node and a second node. A circuit is also included that contains a first circuit and a second circuit. The first circuit is configured to output a first current, which is a multiple of current effectively flowing through the capacitor from the second node to the first node. The second circuit is configured to input a second current, which is a multiple of current effectively flowing through the capacitor from the first node to the second node.

Abstract: An object of the present disclosure is to provide a content addressable memory realizing higher speed of a search access. A content addressable memory includes: a plurality of memory cells; a match line coupled to the plurality of memory cells; a search line coupled to each of the plurality of memory cells; a match line output circuit coupled to the match line; and a potential changing circuit coupled to the match line and changing the potential of the match line.

Abstract: There is to provide a power circuit capable of stabilizing an internal power source voltage and assuring a normal operation of a load circuit. According to one embodiment, the power circuit includes a regulator which generates an output voltage using an entered input voltage, a voltage detecting circuit which detects the output voltage, and a clamp circuit which outputs an internal power source voltage based on the output voltage and in a first failure that the output voltage is larger than a predetermined first voltage, outputs the internal power source voltage suppressed to the first voltage and less, in which the clamp circuit outputs the internal power source voltage to the logic circuit which operates with the internal power source voltage of the first voltage and less and the voltage detecting circuit outputs the first failure to the logic circuit when detecting the first failure.

Abstract: In an active region, a gate electrode is disposed in a trench. Spaced apart from the gate electrode, an emitter electrode is disposed in the trench. A source diffusion layer and a base diffusion layer are formed in the active region. The base diffusion layer has a base bottom portion inclined in such a manner that a portion of the base bottom portion adjacent to the emitter electrode is positionally deeper than a portion of the base bottom portion adjacent to the gate electrode. A contact portion has a contact bottom portion inclined in such a manner that a portion of the contact bottom portion in contact with the emitter electrode is positionally deeper than a portion of the contact bottom portion in contact with the base diffusion layer.

Abstract: When a memory cell is formed over a first fin and a low breakdown voltage transistor is formed over a second fin, the depth of a first trench for dividing the first fins in a memory cell region is made larger than that of a second trench for dividing the second fins in a logic region. Thereby, in the direction perpendicular to the upper surface of a semiconductor substrate, the distance between the upper surface of the first fin and the bottom surface of an element isolation region in the memory cell region becomes larger than that between the upper surface of the second fin and the bottom surface of the element isolation region in the logic region.

Abstract: A logic model of a nonvolatile memory device is commonly used in high order synthesis and a logic simulation. Further, the logic model of the nonvolatile memory device divides a one-time rewriting request area of the nonvolatile memory device into a plurality of areas, and rewrites each of the divided areas in a time division manner.

Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate having a first surface and a second surface which is an opposite surface of the first surface; a first wiring and a second wiring disposed on the first surface; a first conductive film electrically connected to the first wiring; and a gate electrode. The semiconductor substrate has a source region, a drain region, a drift region, and a body region. The drift region is disposed so as to surround the body region in a plan view. The first wiring has a first portion disposed so as to extend across a boundary between the drift region and the body region in a plan view, and electrically connected to the drift region. The second wiring is electrically connected to the source region. The first conductive film is insulated from and faces the second wiring.

Abstract: A semiconductor device whose performance is improved is disclosed. In the semiconductor device, an offset spacer formed in a memory cell is formed by a laminated film of a silicon oxide film and a silicon nitride film, and the silicon oxide film is particularly formed to directly contact the sidewall of a memory gate electrode and the side end portion of a charge storage film; on the other hand, an offset spacer formed in a MISFET is formed by a silicon nitride film. Particularly in the MISFET, the silicon nitride film directly contacts both the sidewall of a gate electrode and the side end portion of a high dielectric constant film.

Abstract: A semiconductor device includes a first field effect transistor and a second field effect transistor which are respectively coupled to gate electrodes. An insulation property of a gate insulating film of the first field effect transistor is broken down. A resistance value of the gate insulating film of the second field effect transistor is greater than a resistance value of the gate insulating film of the first field effect transistor.

Abstract: An apparatus and method for mapping timer channels to protection groups. One embodiment of the method can be implemented in a microcontroller unit (MCU) that comprises a central processing unit (CPU) coupled to a plurality of timer channels and a plurality of programmable group output disable (PTGOD) circuits. The CPU can select a first group of the timer channels to respond to an assertion of a first output disable signal from a first of the PTGOD circuits. Each timer channel of the first group can disable an output signal in response to receiving the assertion of the first output disable signal.

Abstract: A memory access unit for handling transfers of samples in a d-dimensional array between a one of m data buses, where m?1, and k*m memories, where k?2, is disclosed. The memory access unit comprises k address calculators, each address calculator configured to receive a bus address to add a respective offset to generate a sample bus address and to generate, from the sample bus address according to an addressing scheme, a respective address in each of the d dimensions for access along one of the dimensions from the bus address according to an addressing scheme, for accessing a sample. The memory access unit comprises k sample collectors, each sample collector operable to generate a memory select for a one of the k*m memories so as to transfer the sample between a predetermined position in a bus data word and the respective one of the k*m memories.

Abstract: A battery management method and apparatus. In one embodiment of the method, a source current is divided into Ic and Icr. Ic is transmitted to and charges a battery. A first voltage is generated that is related to Icr. The first voltage is converted into a first digital signal. A processing unit receives and processes the first digital signal in accordance with instructions stored in a memory. The transmission of Ic to the battery is interrupted in response to the processing unit processing the first digital signal. Current provided by the battery is divided into Idc and Idcr. Idc is transmitted to a device. A second voltage is generated that is related to Idcr. The second voltage is converted into a second digital signal. The processing unit receives and processes the second digital signal in accordance with instructions stored in the memory. The transmission of Idc to the battery is interrupted in response to the processing unit processing the second digital signal.

Abstract: A buck boost converter includes a buck boost converter circuit to generate an output voltage in response to an input voltage, and a mode control logic circuit to generate a mode control signal to control an operation mode of the buck boost converter circuit to operate in one of a buck mode, a boost mode, and a buck-boost mode. The buck boost converter circuit includes an upper buck transistor coupled to an input voltage node, the input voltage node to receive the input voltage, an upper boost transistor coupled to an output voltage node, the output voltage node to output the output voltage, and an inductor coupled between the upper buck transistor and the upper boost transistor. The mode control signal is generated based on a first duty cycle of the upper buck transistor and a second duty cycle of the upper boost transistor.

Abstract: Provided are a wireless communication apparatus, a system and a method that are suitable for establishing steady communication by using a redundant configuration. The wireless communication apparatus includes a plurality of devices that transmit and receive data through a wireless network. The devices each include a control section and a decision section. The decision section in one of the devices designates a first device from among the devices as a first valid device, and designates a second device as a second valid device. The control section in the first device copies to the second device the data and coupling information for transmitting and receiving the data. When the second device is determined to valid, the control section in the second device transmits the copied data from the second device.

Abstract: To improve the reliability of a semiconductor device. The semiconductor device includes a plurality of wiring layers formed on a semiconductor substrate, a pad formed on an uppermost wiring layer of the plurality of wiring layers, a surface protection film which includes an opening on the pad and is made of an inorganic insulating film, a rewiring formed on the surface protection film; a pad electrode formed on the rewiring, and a wire connected to the pad electrode. The rewiring includes a pad electrode mounting portion on which the pad electrode is mounted, a connection portion which is connected to the pad, and an extended wiring portion which couples the pad electrode mounting portion and the connection portion, and the pad electrode mounting portion has a rectangular shape when seen in a plan view.

Abstract: An apparatus includes a package and a beam former circuit. The package may be configured to be mounted on an antenna array at a center of four antenna elements. Each antenna element may include a dual-pole antenna having a vertical feed and a horizontal feed. The beam former circuit may be (i) disposed in the package, (ii) have a plurality of pairs of ports, (iii) configured to generate a plurality of radio-frequency signals in the ports while in a transmit mode and (iv) configured to receive the radio-frequency signals at the ports while in a receive mode. Each pair of the ports is configured to be directly connected to a respective one of the antenna elements. All of the ports may be spatially routed into alignment with the vertical feeds and the horizontal feeds in a single conductive plane of the antenna array.

Abstract: An apparatus includes a plurality of conductive layers and a plurality of traces configured to carry a plurality of signals through a change of direction. The traces may be routed parallel to each other in a first trace segment in a first of the conductive layers toward the change of direction. The traces may be routed parallel to each other in a second trace segment in a second of the conductive layers in the change of direction. One of the traces in a third trace segment in the first conductive layer may cross over another of the traces in the second trace segment in the second conductive layer in the change of direction. The traces may be routed parallel to each other in the third trace segment in the first conductive layer away from the change of direction.