Abstract: A receiving circuit, a transmission circuit and a system capable of reducing the effect of noise are provided. The receiving circuit includes: a pulse width detection unit which determines whether or not the pulse width of a pulse signal outputted based on comparison between a received-signal voltage and a reference voltage is smaller than a predetermined width; a reference voltage setting unit which, when the pulse width is smaller than the predetermined width, sets the reference voltage to be equal to or higher than a predetermined voltage; and an output control unit which, when the pulse width is equal to or larger than the predetermined width, causes a digital signal based on the pulse signal to be outputted or, when the pulse width is smaller than the predetermined width, performs control not to output the digital signal.

Abstract: A semiconductor device includes: a first cell; a second cell; a first match line and a second match line; a first search line pair, first data being transmitted through the first search line pair; a second search line pair, second data being transmitted through the second search line pair; a first logical operation cell connected to the first search line pair and the first match line, and configured to drive the first match line based on a result of comparison between information held by the first and second cells and the first data; and a second logical operation cell connected to the second search line pair and the second match line, and configured to drive the second match line based on a result of comparison between information held by the first and second cells and the second data.

Abstract: One or more embodiments are directed to a multiport power delivery architecture that reduces the cost and maximize the power utilization. According to some aspects, embodiments solve problems associated with charging a battery with multiple adapter. Some embodiments enable supplying system load and charging a battery from two or more adapters simultaneously through a single sensing resistor.

Abstract: A CPU needs to perform reset operation when a secondary arithmetic processing unit controlled by the CPU controls a signal processing circuit. CPU A controls module A. CPU B controls module B. Module A and module B control a signal processing circuit. CPU A and CPU B issue a reset request to the signal processing circuit. The signal processing circuit performs a reset process based on the reset request accepted from the CPU and a control origin identification signal that identifies a CPU as an origin of controlling the module having started a signal processing section.

Abstract: A connector of a battery device includes a first terminal and a second terminal. The first terminal is coupleable to an opposed unit through a cable in a first state. The second terminal is coupleable to the opposed unit through the cable in the second state which is inverted upside down from the first state. A control device of the battery device is configured to charge the battery device with electric power from the opposed unit, when it is coupled to the opposed unit through the cable in the first state, and to supply the opposed unit with electric power from the battery device, when it is coupled to the opposed unit through the cable in the second state.

Abstract: There is a need to detect faults on a path between a memory access circuit and a shared resource, faults in a logic circuit, and faults in the shared resource. A semiconductor device includes: a first memory access circuit; a second memory access circuit to check the first memory access circuit; a memory that outputs a memory address based on a first access address input from the first memory access circuit; a duplexing comparison circuit that compares the first access address with a second access address output from the second memory access circuit; a first address comparison circuit that compares the first access address with the memory address; and an error control circuit that outputs a control signal based on a comparison result from the duplexing comparison circuit and a comparison result from the first address comparison circuit.

Abstract: An object of the present invention is to efficiently compress a plurality of kinds of data series with different sampling rates. A data compression device has a grouping unit and a compression unit. The grouping unit groups a plurality of kinds of data series with different sampling rates. The compression unit compresses the data series grouped by the grouping unit.

Abstract: A semiconductor device including an image sensor device controlled by an adjusting circuit, and the adjusting circuit configured to transmit a control signal to the image sensor device to be controlled according to a transmission cycle synchronized with a reference clock, the image sensor device includes a first period during which the control signal is allowed to be supplied to the image sensor device to be controlled and a second period during which the supplying of the control signal to the image sensor device to be controlled is not preferable compared to that in the first period, the adjusting circuit is configured to, when a transmission timing of the control signal determined according to the transmission cycle is within the second period, adjust the transmission timing of the control signal so that the control signal will be transmitted in the first period to the image sensor device.

Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

Abstract: In order to easily sort failures due to short circuit between wires in an inductor, a semiconductor device includes a plurality of inductors (first inductor, second inductor) formed in a plurality of wiring layers. In each of the wiring layers, the metal layer of the first inductor and the metal layer of the second inductor respectively extend around the peripheral region from the inner periphery to the outer periphery in the same direction. The metal layer of the first inductor and the metal layer of the second inductor are arranged so as to be adjacent to each other.

Abstract: To provide an information processing apparatus, a reading control method, and a computer readable storage medium that can improve the secrecy of information written in a secret area compared with the case of controlling access only by authentication, the information processing apparatus includes a nonvolatile memory that has a secret area where secret information is stored, an authentication controller that authenticates access to the nonvolatile memory, a flag information storage unit that stores flag information, and a memory controller that controls access to the nonvolatile memory by using the flag information stored in the flag information storage unit. The memory controller allows reading of the secret information from the secret area when a value of the flag information is a specified value and validity of access is authenticated by the authentication controller.

Abstract: A device for open load diagnosis of a signal line in a digital system in which a logic state is represented by a band of voltages lying between first and second voltage limits is described. The device is configured to cause the signal line to reach a first, stable voltage lying in the band, to apply a second, different voltage to the signal line lying in the band and without leaving the band, to perform a time constant dependent measurement so as to determine a value of a parameter which is or depends on resistance of a load between the signal line and a reference line, to compare the value of the parameter with a reference value of the parameter and, in dependence on comparison, to signal the result.

Abstract: A battery authentication system includes a battery pack, and a host device connected to the battery pack to charge the battery pack. The battery pack includes a battery, a discharge switch that turns on and off discharging of the battery, a charge switch that turns on and off charging of the battery, and a control integrated circuit (IC) that controls the battery. The control IC includes a charge/discharge control circuit that controls the discharge switch and the charge switch, and an authentication circuit that performs a process for performing an authentication with the host device. The authentication circuit is configured to perform a process associated with a first authentication. The charge/discharge control circuit is configured to control the discharge switch to be turned on when the first authentication is established. The authentication circuit is configured to perform a process associated with a second authentication.

Abstract: Regarding association between an area where compressed data is stored and an area where auxiliary information required to access the compressed data is stored, it is necessary to manage the association by software for each processing unit, so that the processing becomes complicated. A management unit memory area including a compressed data storage area and an auxiliary information storage area including auxiliary information are defined on a memory space. By calculating an auxiliary information address from an address indicating a location on a memory where a management unit memory space is set, an address of the auxiliary information storage area, and an address of the compressed data, the compressed data and the auxiliary information are associated with each other and the auxiliary information is read.

Abstract: A semiconductor device is provided that operates at improved write speeds without an increase in area. The semiconductor device according to the invention includes a plurality of memory cells arranged in a matrix of rows and columns, a plurality of word lines provided to each row of the memory cells, a plurality of bit line pairs provided to each column of the memory cells, sense amplifiers that amplify the potential difference in the bit line pairs, data line pairs that transfer data to the bit line pairs, column selection circuits that permit receiving the data from the data line pairs, a column decoder that transmits column selection signals to the column selection circuits, and a sense amplifier control circuit that activates the sense amplifiers after the column decoder transmits the column selection signals to the column selection circuits.

Abstract: The sampling data signal and the sampling synchronizing clock are generated by sampling the data signal and the synchronizing clock, and the first driving pulse signal and the second driving pulse signal are generated based on the sampling data signal and the sampling synchronizing clock, and the isolator is driven by the first driving pulse signal and the second driving pulse signal.

Abstract: One or more embodiments enable both a fixed bandgap reference voltage and a variable reference voltage to be generated and stored on a capacitor. According to certain aspects, the present embodiments use an additional storage capacitor of smaller size to reduce the sub-threshold leakage of an isolating FET switches at high temperatures. Among other aspects, this enables a more efficient use of chip area for reducing sub-threshold induced leakage than simply increasing the storage capacitor when precision storage is required.

Abstract: A semiconductor device includes a first semiconductor chip having a first inductor element and a second inductor element on a first main surface side, a second semiconductor chip having a third inductor element on a second main surface side, and a third semiconductor chip having a fourth inductor element on a third main surface side. The first and second inductor elements are arranged to be separated from each other in a first direction of the first main surface, the first and second main surfaces face each other, and the first and third inductor elements overlap each other. The first and third main surfaces face each other, the second and fourth inductor elements overlap each other, and a creepage distance between the second and third semiconductor chips is larger than a separation distance between the second and third semiconductor chips.

Abstract: Even when a driven circuit has a large-scale load, a small-scale step-down driver circuit can supply an internal potential to the driven circuit at high speed. A semiconductor integrated circuit device includes a step-down driver circuit which supplies, to a driven circuit to be driven by an internal potential lower than an external potential supplied from an external power supply, the internal potential. The step-down driver circuit includes an NMOS transistor having a drain coupled to an external power supply terminal to be coupled to the external power supply and a source to be coupled to a voltage supply point of the driven circuit and a driver circuit to drive the gate of the NMOS transistor.

Abstract: The reliability of a semiconductor device is improved. A photoresist pattern is formed over a semiconductor substrate. Then, over the semiconductor substrate, a protective film is formed in such a manner as to cover the photoresist pattern. Then, with the photoresist pattern covered with the protective film, an impurity is ion implanted into the semiconductor substrate. Thereafter, the protective film is removed by wet etching, and then, the photoresist pattern is removed.