Abstract: This disclosure includes embodiments of a radio frequency (RF) transceiver having a distributed duplex filtering topology. The RF transceiver includes a power amplifier and a tunable RF duplexer. The tunable RF duplexer is configured to input an RF transmission input signal from the power amplifier, generate an RF transmission output signal that operates within an RF transmission band in response to the RF transmission input signal from the power amplifier, and simultaneously output the RF transmission output signal to an antenna and input an RF receive input signal that operates within an RF receive band from the antenna. The power amplifier includes a plurality of RF amplifier stages coupled in cascode and an RF filter coupled between a first one of the RF amplifier stages and a second one of the RF amplifier stages. Accordingly, the RF filter is configured to provide tuning within the RF receive band.

Abstract: An efficient power transfer power amplifier (PA) architecture is disclosed that includes a first PA, a first impedance transformation network (ITN) coupled to the first PA, a second PA, and a second ITN coupled to the second PA. A switching network having a plurality of load outputs along with a first switch input coupled to a first impedance output of the first ITN and a second switch input coupled to a second impedance output of the first ITN, a third switch input coupled to a third impedance output of the second ITN, and a fourth switch input coupled to a fourth impedance output of the second ITN. A control system is adapted to control the switching network to switch signals at the first, second, third, and fourth switch inputs such that select ones of the signals travel paths having matching impedances to loads coupled to the plurality of load outputs.

Abstract: The present invention provides a multiple gate transistor architecture that provides an accessible inner source-drain (SD) node. The transistor architecture includes a source structure having multiple source fingers, which extend from a source bus, and a drain structure having multiple drain fingers, which extend from a drain bus. The fingers of the respective source and drain structures are interleaved wherein a meandering path is formed between the source and drain structures. Two or more gate structures run substantially parallel to one another along the meandering path between the source and drain structures. An SD structure is provided between each adjacent pair of gate structures and runs along the meandering path to form the SD node. An SD extension is coupled to the SD structure and accessible by other circuitry to allow a signal to be applied to the SD structure during operation.

Abstract: A radio frequency (RF) communications system, which includes an RF power amplifier (PA) and an envelope tracking power supply, is disclosed. The RF communications system processes RF signals associated with at least a first RF communications band, which has a first bandwidth. The RF PA receives and amplifies an RF input signal to provide an RF transmit signal using an envelope power supply signal. The envelope tracking power supply provides the envelope power supply signal, which has switching ripple based on a programmable switching frequency. The programmable switching frequency is selected to be greater that the first bandwidth.

Abstract: Two Manchester encoded bit streams each bit stream with accompanying embedded clock data are disclosed. The two encoded bit streams are encoded at the source using opposite polarities of the source clock to position transitions within the bit streams at the rising and falling edges of the source clock. The receiver may extract the clock data from both bit streams. Because both rising and falling edge clock data is available between the two bit streams, the receiver does not need a phase locked loop (PLL) or incur the accompanying expense of such PLL. Further, by avoiding use of a PLL, a nearly all digital circuit may be created, which may provide further cost and space savings. Still further, a higher data throughput is provided without increasing pin count or signal bandwidth.

Abstract: Radio Frequency (RF) signal conditioning circuitry, which includes RF detection circuitry and RF attenuation circuitry is disclosed. The RF detection circuitry receives and detects an RF sample signal to provide an RF detection signal. The RF attenuation circuitry has an attenuation circuitry input, and receives and attenuates the RF sample signal via the attenuation circuitry input to provide an attenuated RF signal. The RF attenuation circuitry presents an attenuation circuitry input impedance at the attenuation circuitry input. The attenuated RF signal and the RF detection signal are provided concurrently.

Abstract: A tunable radio frequency (RF) duplexer and duplexing methods are disclosed. The tunable RF duplexer includes a first hybrid coupler, a second hybrid coupler, and an RF filter circuit. The first hybrid coupler is operable to split the RF transmission input signal into first and second RF quadrature hybrid transmission signals (QHTSs). The second hybrid coupler is operable to split the RF receive input signal into first and second RF quadrature hybrid receive signals (QHRSs). The RF filter circuit is operable to pass the first and second RF QHTSs to the second hybrid coupler and to reflect the first and second RF QHRSs back to the second hybrid coupler. Additionally, the second hybrid coupler is configured to combine the first and second RF QHTSs into an RF transmission output signal and to combine the first and second RF QHRSs into an RF receive output signal.

Abstract: Differential power amplifier circuitry includes a differential transistor pair, an input transformer, and biasing circuitry. The base contact of each transistor in the differential transistor pair may be coupled to the input transformer through a coupling capacitor. The coupling capacitors may be designed to resonate with the input transformer about a desired frequency range, thereby passing desirable signals to the differential transistor pair while blocking undesirable signals. The biasing circuitry may include a pair of emitter follower transistors, each coupled at the emitter to the base contact of each one of the transistors in the differential transistor pair and adapted to bias the differential transistor pair to maximize efficiency and stability.

Abstract: This disclosure relates to radio frequency (RF) power converters and methods of operating the same. In one embodiment, an RF power converter includes an RF switching converter, a low-drop out (LDO) regulation circuit, and an RF filter. The RF filter is coupled to receive a pulsed output voltage from the RF switching converter and a supply voltage from the LDO regulation circuit. The RF filter is operable to alternate between a first RF filter topology and a second RF filter topology. In the first RF filter topology, the RF filter is configured to convert the pulsed output voltage from a switching circuit into the supply voltage. The RF filter in the second RF filter topology is configured to filter the supply voltage from the LDO regulation circuit to reduce a ripple variation in a supply voltage level of the supply voltage. As such, the RF filter provides greater versatility.

Abstract: This disclosure relates to radio frequency (RF) power converters and methods of operating the same. In one embodiment, an RF power converter includes an RF switching converter, a low-drop out (LDO) regulation circuit, and an RF filter. The RF filter is coupled to receive a pulsed output voltage from the RF switching converter and a supply voltage from the LDO regulation circuit. The RF filter is operable to alternate between a first RF filter topology and a second RF filter topology. In the first RF filter topology, the RF filter is configured to convert the pulsed output voltage from a switching circuit into the supply voltage. The RF filter in the second RF filter topology is configured to filter the supply voltage from the LDO regulation circuit to reduce a ripple variation in a supply voltage level of the supply voltage. As such, the RF filter provides greater versatility.

Abstract: A tunable radio frequency (RF) duplexer is disclosed. The tunable RF duplexer includes a first hybrid coupler, a second hybrid coupler, and an RF filter circuit. The first hybrid coupler is operable to split an RF receive input signal into first and second RF quadrature hybrid receive signals (QHRSs). The first hybrid coupler is also operable to split an RF transmission input signal into first and second RF quadrature hybrid transmission signals (QHTSs). The RF filter circuit is operable to pass the first and second RF QHRSs to the second hybrid coupler and to reflect the first and second RF QHTSs back to the first hybrid coupler. Additionally, the second hybrid coupler is configured to combine the first and second RF QHRSs into an RF receive output signal, while the first hybrid coupler is configured to combine the first and second RF QHTSs into an RF transmission output signal.

Abstract: This disclosure relates generally to radio frequency (RF) amplification devices and methods of limiting an RF signal current. Embodiments of the RF amplification device include an RF amplification circuit and a feedback circuit. The RF amplification circuit is configured to amplify an RF input signal so as to generate an amplified RF signal that provides an RF signal current with a current magnitude. The feedback circuit is used to limit the RF signal current. In particular, a thermal sense element in the feedback circuit is configured to generate a sense current, and thermal conduction from the RF amplification circuit sets a sense current level of the sense current as being indicative of the current magnitude of the RF signal current. To limit the RF signal current, the feedback circuit decreases the current magnitude of the RF signal current in response to the sense current level reaching a trigger current level.

Abstract: Embodiments of the present disclosure relate to an overlay class F choke of a radio frequency (RF) power amplifier (PA) stage and an RF PA amplifying transistor of the RF PA stage. The overlay class F choke includes a pair of mutually coupled class F inductive elements, which are coupled in series between a PA envelope power supply and a collector of the RF PA amplifying transistor. In one embodiment of the RF PA stage, the RF PA stage receives and amplifies an RF stage input signal to provide an RF stage output signal using the RF PA amplifying transistor. The collector of the RF PA amplifying transistor provides the RF stage output signal. The PA envelope power supply provides an envelope power supply signal to the overlay class F choke. The envelope power supply signal provides power for amplification.

Abstract: The present disclosure relates to envelope power supply calibration of a multi-mode RF power amplifier (PA) to ensure adequate headroom when operating using one of multiple communications modes. The communications modes may include multiple modulation modes, a half-duplex mode, a full-duplex mode, or any combination thereof. As such, each communications mode may have specific peak-to-average power and linearity requirements for the multi-mode RF PA. As a result, each communications mode may have corresponding envelope power supply headroom requirements. The calibration may include determining a saturation operating constraint based on calibration data obtained during saturated operation of the multi-mode RF PA. During operation of the multi-mode RF PA, the envelope power supply may be restricted to provide a minimum allowable magnitude based on an RF signal level of the multi-mode RF PA, the communications mode, and the saturation operating constraint to provide adequate headroom.

Abstract: A direct current (DC)-DC converter, which includes switching circuitry, a first parallel amplifier, and a second parallel amplifier, is disclosed. The switching circuitry has a switching circuitry output. The first parallel amplifier has a first feedback input and a first parallel amplifier output. The second parallel amplifier has a second feedback input and a second parallel amplifier output. A first inductive element is coupled between the switching circuitry output and the first feedback input. A second inductive element is coupled between the first feedback input and the second feedback input.

Abstract: The present disclosure relates to envelope power supply calibration of a multi-mode RF power amplifier (PA) to ensure adequate headroom when operating using one of multiple communications modes. The communications modes may include multiple modulation modes, a half-duplex mode, a full-duplex mode, or any combination thereof. As such, each communications mode may have specific peak-to-average power and linearity requirements for the multi-mode RF PA. As a result, each communications mode may have corresponding envelope power supply headroom requirements. The calibration may include determining a saturation operating constraint based on calibration data obtained during saturated operation of the multi-mode RF PA. During operation of the multi-mode RF PA, the envelope power supply may be restricted to provide a minimum allowable magnitude based on an RF signal level of the multi-mode RF PA, the communications mode, and the saturation operating constraint to provide adequate headroom.

Abstract: Combination circuitry includes a relatively small preamplifier and includes hybrid circuitry. The hybrid circuitry is configured to perform mode switching while also performing some amplification, thus allowing the relatively small preamplifier to be smaller than a conventional power amplifier. In one embodiment, the hybrid circuitry includes first series portion configured to amplify when ON, a first shunt portion, a second series portion configured to amplify when ON, and a second shunt portion. The first series portion may include: a first transistor; a first variable impedance in communication with a gate of the first transistor, wherein the first variable impedance is configured to receive a first transistor control signal; a second transistor in series with the first transistor; and a second variable impedance in communication with a gate of the second transistor, wherein second variable impedance is configured to receive a second transistor control signal.

Abstract: A transceiver may include an antenna tuning control system operably associated with an antenna tuner to control the current power levels of the transmission signal and the receive signal. The antenna tuner control system may receive transmit power control (TPC) information, which was transmitted to the transceiver from a base station on the receive signal. The TPC information may be utilized to change the current power level of the transmission signal to a desired transmission power level. In addition, the antenna tuner control system may generate receive power control (RPC) information. The RPC information may be utilized to change the current power level of the receive signal to a desired receive power level. The antenna tuner control system is operable to adjust the pass band in accordance with the TPC information and the RPC information.

Abstract: A parallel amplifier, a switching supply, and a radio frequency (RF) notch filter are disclosed. The parallel amplifier has a parallel amplifier output, such that the switching supply is coupled to the parallel amplifier output. Further, the RF notch filter is coupled between the parallel amplifier output and a ground. The RF notch filter has a selectable notch frequency, which is based on an RF duplex frequency.

Abstract: A method for power amplifier (PA) calibration for an envelope tracking system of a wireless device is disclosed. The method involves measuring an output power of a PA that is a part under test (PUT) at a predetermined input power. Another step includes calculating a gain equal to the output power of the PA divided by the predetermined input power. A next step involves calculating a gain correction by subtracting the calculated gain from a desired gain. Other steps include determining an expected supply voltage for the PA at the desired gain using the gain correction applied to a nominal curve of gain versus PA supply voltage, and then storing the expected supply voltage for the PA versus input power in memory.