Abstract: There is provided a semiconductor device that includes a wiring layer having a main surface and a rear surface which face opposite sides in a thickness direction, a first insulating layer covering an entirety of the rear surface, a second insulating layer which is in contact with the main surface, a semiconductor element which faces the second insulating layer and is mounted on the wiring layer, and a sealing resin which is in contact with the second insulating layer and covers the semiconductor element, wherein surface roughness of the main surface is larger than surface roughness of the rear surface.

Abstract: The present disclosure provides a power supply control device. The power supply control device includes a feedback voltage generator, an on-timing setting unit and an off-timing setting unit. The feedback voltage generator is configured to generate a feedback voltage by sampling a primary voltage of a transformer that forms an insulated switching power supply. The on-timing setting unit is configured to turn on a primary current of the transformer based on a comparison result between the feedback voltage and a slope-shaped reference voltage. The off-timing setting unit is configured to turn off the primary current after a predetermined on time has elapsed since the primary current was turned on. A sampling timing of the primary voltage is set based on an on timing of the primary current.

Abstract: An apparatus includes a control device configured to serve as a principal controlling agent in an electric power conversion device incorporating a switching circuit configured to be a bidirectional inverter. The control device is configured to subtract, from a reference signal that is determined in accordance with an operation mode of the electric power conversion device, a multiplied signal obtained by multiplying a control-target current of the switching circuit by a prescribed coefficient to generate, based on a result of the subtraction, a control signal for controlling the bidirectional inverter.

Abstract: This light-emitting element drive control device (100) comprises: a drive logic unit (113) which performs a drive control of a switch output stage (N1, D1, L1) for dropping an input voltage (VIN) to an output voltage (VOUT) and supplying a light-emitting element therewith: a charge-pump power supply unit (?) which generates a step-up voltage (CP) higher than the input voltage (VIN); and a current detecting comparator (114) which receives a supply of the step-up voltage (CP) and the output voltage (VOUT) as power supply voltages, and generates control signals (SET, RST) for the drive logic unit (113) by directly comparing a current detection signal (Vsns) corresponding to an inductor current (IL) of the switch output stage with a peak detection value (Vsns_pk) and a bottom detection value (Vsns_bt).

Abstract: A semiconductor device includes first and second insulated-gate transistors in parallel with each other, a charger-discharger, and a gate voltage correction circuit. The charger-discharger can perform first control to charge both of the gates of the first and second transistors, second control to discharge both of the gates of the first and second transistors, and third control to charge one of the gates of the first and second transistors. The gate voltage correction circuit corrects the gate voltages of the first and second transistors to eliminate the difference between those voltages in at least one of the first control, the second control, and protection operation in which the first and second transistors are forcibly kept off.

Abstract: A semiconductor device includes a semiconductor substrate having a principal surface, a semiconductor layer formed on the principal surface of the semiconductor substrate, the semiconductor layer including a first-conductivity-type low concentration layer in contact with the principal surface of the semiconductor substrate and a first-conductivity-type high concentration layer that is formed at a surface layer portion of a surface, which is on a side opposite to the principal surface, of the semiconductor layer and that has a higher impurity concentration than the low concentration layer, and a Schottky electrode that is formed on the surface of the semiconductor layer and that forms a Schottky junction portion between the high concentration layer and the Schottky electrode.

Abstract: Provided is a load drive device comprising: a first input terminal for accepting an input of a first input current from a power source; a second input terminal for accepting an input of a second input current from the power source via an external resistor; an output terminal for outputting an output current to a load; a current distribution unit for summing the first input current and second input current at a prescribed distribution ratio and generating the output current and a control unit for controlling the distribution ratio. As one example, it would be appropriate for the control unit to control the distribution ratio according to the difference between a first terminal voltage present in the second input terminal and a second terminal voltage present in the output terminal.

Abstract: Disclosed is a production system for methane, including a reaction vessel having a solid electrolyte membrane and an electrode group including at least a pair of electrodes arranged on the solid electrolyte membrane, in which one of the electrodes functions as a cathode side electrode, and the other electrode functions as an anode side electrode, and the one electrode that functions as the cathode side electrode includes a hydrogenation catalyst.

Abstract: A wide band gap semiconductor device includes a semiconductor layer, a trench formed in the semiconductor layer, first, second, and third regions having particular conductivity types and defining sides of the trench, and a first electrode embedded inside an insulating film in the trench. The second region integrally includes a first portion arranged closer to a first surface of the semiconductor layer than to a bottom surface of the trench, and a second portion projecting from the first portion toward a second surface of the semiconductor layer to a depth below a bottom surface of the trench. The second portion of the second region defines a boundary surface with the third region, the boundary region being at an incline with respect to the first surface of the semiconductor layer.

Abstract: A mirror clamp circuit includes a comparator having a first input terminal connectable to a first control terminal of a transistor having the first control terminal connected to the other terminal of a resistor of which one terminal is fed with an output voltage and a first terminal fed with a reference potential and a second input terminal fed with a reference voltage, a transistor switch having a second control terminal fed with a control terminal voltage based on a comparison signal output from the comparator and inserted between the first control terminal and the reference potential, an OR circuit fed with a signal based on the control terminal voltage and the output voltage, and a current feeder configured to change the amount of current fed to the comparator based on the output of the OR circuit.

Abstract: A semiconductor device includes a semiconductor layer having a first main surface on one side and a second main surface on the other side, a unit cell including a diode region of a first conductivity type formed in a surface layer portion of the first main surface of the semiconductor layer, a well region of a second conductivity type formed in the surface layer portion of the first main surface of the semiconductor layer along a peripheral edge of the diode region, and a first conductivity type region formed in a surface layer portion of the well region, a gate electrode layer facing the well region and the first conductivity type region through a gate insulating layer and a first main surface electrode covering the diode region and the first conductivity type region on the first main surface of the semiconductor layer, and forming a Schottky junction with the diode region and an ohmic junction with the first conductivity type region.

Abstract: An electronic component includes an insulating layer that has a principal surface, a passive device that includes a low voltage pattern that is formed in the insulating layer and a high voltage pattern that is formed in the insulating layer such as to oppose the low voltage pattern in a normal direction to the principal surface and to which a voltage exceeding a voltage to be applied to the low voltage pattern is to be applied, and a shield conductor layer that is formed in the insulating layer such as to be positioned in a periphery of the high voltage pattern in plan view, shields an electric field formed between the low voltage pattern and the high voltage pattern, and suppresses electric field concentration with respect to the high voltage pattern.

Abstract: There is provided a semiconductor device, including: a semiconductor element which includes an element main surface and an element rear surface that face opposite sides in a thickness direction and in which a first electrode and a second electrode are formed on the element main surface; a first conductive member electrically connected to the first electrode; a second conductive member electrically connected to the second electrode; and a sealing resin configured to cover part of the first conductive member, part of the second conductive member, and the semiconductor element.

Abstract: A semiconductor device includes a first die pad, a second die pad, a first semiconductor element, a second semiconductor element, an insulating element, first terminals, second terminals, and a sealing resin. The sealing resin has a top surface, a bottom surface, and first to third side surfaces. The first terminals include a first edge terminal located closest to the third side surface. The second terminals include a second edge terminal located closest to the third side surface. A first creepage distance, which is a shortest distance from the first edge terminal to the second edge terminal along the first side surface, the third side surface, and the second side surface, is shorter than a second creepage distance, which is a shortest distance from the first edge terminal to the second edge terminal along the first side surface, the bottom surface, and the second side surface.

Abstract: A resistor includes a resistive element, an insulation plate, a protective film, and a pair of electrodes. The resistive element includes a first face and a second face arranged to face in opposite directions in a thickness direction. The insulation plate is on the first face, and the protective film on the second face. The electrodes are spaced apart in a first direction perpendicular to the thickness direction, and held in contact with the resistive element. Each electrode includes a bottom portion opposite to the insulation plate with respect to the resistive element in the thickness direction. Each bottom portion overlaps with a part of the protective film as viewed in the thickness direction. The resistor further includes a pair of intermediate layers spaced apart in the first direction. The intermediate layers are formed of a material electrically conductive and containing a synthetic resin. Each intermediate layer includes a cover portion covering a part of the protective film.

Abstract: A semiconductor device includes a semiconductor element, a first lead supporting the semiconductor element, a second lead separated from the first lead, and a connection lead electrically connecting the semiconductor element to the second lead. The connection lead has an end portion soldered to the second lead. This connection-lead end portion has a first surface facing the semiconductor element and a second surface opposite to the first surface. The second lead is formed with a recess that is open toward the semiconductor element. The recess has a side surface facing the second surface of the connection-lead end portion. A solder contact area of the second surface of the connection-lead end portion is larger than a solder contact area of the first surface of the connection-lead end portion.

Abstract: A method for manufacturing a semiconductor device includes a step of preparing a semiconductor wafer source which includes a first main surface on one side, a second main surface on the other side and a side wall connecting the first main surface and the second main surface, an element forming step of setting a plurality of element forming regions on the first main surface of the semiconductor wafer source, and forming a semiconductor element at each of the plurality of element forming regions, and a wafer source separating step of cutting the semiconductor wafer source from a thickness direction intermediate portion along a horizontal direction parallel to the first main surface, and separating the semiconductor wafer source into an element formation wafer and an element non-formation wafer after the element forming step.

Abstract: A piezoelectric element 10 includes a lower electrode, constituted of a Pt/Ti laminated film, a PLT seed layer, formed on the lower electrode, a PZT piezoelectric film, formed on the PLT seed layer, and an upper electrode, formed on the PZT piezoelectric film. A curve Q1 is a curve drawn such as to pass through a plurality of plotted points, each expressing a PLT (100) peak intensity with respect to a Pt (111) peak intensity according to a substrate setting temperature during forming of the Pt/Ti laminated film. A relationship of the PLT (100) peak intensity with respect to the Pt (111) peak intensity is within a range in the curve Q1 until the PLT (100) peak intensity decreases by 5% from a peak point P, at which the PLT (100) peak intensity is the maximum, and a (100) orientation rate of PLT constituting the seed layer is not less than 85%.

Abstract: Disclosed are a switch driving device, in which individual zero voltage switching control of a first switch element and a second switch element forming a bidirectional switch is performed, and a switching power supply including a primary winding to which an alternating-current input voltage is applied, a secondary winding electromagnetically coupled to the primary winding, the bidirectional switch connected in series with the primary winding, a resonance capacitor connected in parallel with at least one of the bidirectional switch and the primary winding, a full-wave rectifier circuit that performs full-wave rectification of an induced voltage occurring in the secondary winding, a smoothing capacitor that smooths output of the full-wave rectifier circuit, and the switch driving device that drives the bidirectional switch.

Abstract: A zero-crossing detection circuit includes a zero-crossing detection unit arranged to compare a first monitoring target signal and a second monitoring target signal respectively input through diodes from a first node and a second node between which an AC signal is applied, so as to generate a first comparison signal, and a logic unit arranged to estimate a zero cross of the AC signal from the first comparison signal so as to generate a zero-crossing detection signal. The zero-crossing detection circuit preferably includes a monitoring unit arranged to adjust the first monitoring target signal and the second monitoring target signal to be suitable for input to the zero-crossing detection unit. The logic unit preferably counts a period of the first comparison signal and estimates a zero cross of the AC signal using a count value thereof.