Abstract: A semiconductor device includes a semiconductor element including a transistor, a gate interconnect electrically connected to a gate electrode and extending in a first direction, two connection pads electrically connected to a source or drain electrode and separated in a second direction orthogonal to the first direction in plan view, a passivation layer formed on the gate interconnect, and an organic film layer formed on the passivation layer, a conductive bonding material disposed on the semiconductor element and at least partially overlapping the gate interconnect and the connection pads in plan view, and a conductive member disposed on the conductive bonding material. The connection pads are electrically connected to the conductive member via the conductive bonding material. The gate interconnect is disposed between the connection pads in plan view. The passivation layer is separated from the conductive bonding material by the organic film layer being thicker than the passivation layer.

Abstract: A wide band gap semiconductor device includes a semiconductor layer, a trench formed in the semiconductor layer, first, second, and third regions having particular conductivity types and defining sides of the trench, and a first electrode embedded inside an insulating film in the trench. The second region integrally includes a first portion arranged closer to a first surface of the semiconductor layer than to a bottom surface of the trench, and a second portion projecting from the first portion toward a second surface of the semiconductor layer to a depth below a bottom surface of the trench. The second portion of the second region defines a boundary surface with the third region, the boundary region being at an incline with respect to the first surface of the semiconductor layer.

Abstract: A method for manufacturing a semiconductor device includes a step of preparing a semiconductor wafer source which includes a first main surface on one side, a second main surface on the other side and a side wall connecting the first main surface and the second main surface, an element forming step of setting a plurality of element forming regions on the first main surface of the semiconductor wafer source, and forming a semiconductor element at each of the plurality of element forming regions, and a wafer source separating step of cutting the semiconductor wafer source from a thickness direction intermediate portion along a horizontal direction parallel to the first main surface, and separating the semiconductor wafer source into an element formation wafer and an element non-formation wafer after the element forming step.

Abstract: A semiconductor device includes a chip, a drain region, a source region formed at the surface layer portion of the main surface at a distance from the drain region, a channel inversion region formed on a side of the source region between the drain region and the source region in the surface layer portion of the main surface, a drift region formed in a region between the drain region and the channel inversion region in the surface layer portion of the main surface, a gate insulating film having a first portion that covers the channel inversion region on the main surface and a second portion that covers the drift region on the main surface, and a gate electrode having a first electrode portion covering the first portion and a second electrode portion led out from the first electrode portion onto second portion so as to partially expose second portion.

Abstract: A resistor includes a first insulator, a resistive body, a second insulator, a pair of electrodes, and a covering body. The first insulator has a first obverse surface facing in a thickness direction thereof. The resistive body is provided on the first obverse surface. The second insulator covers the resistive body. The pair of electrodes are electrically connected to the resistive body at both sides in a first direction perpendicular to the thickness direction. The covering body is formed on at least one of the first insulator and the second insulator. The covering body has electrical conductivity. The first layer is in contact with at least one of the first insulator and the second insulator.

Abstract: A light receiving element array includes a substrate and a laminated semiconductor structure that is formed on the substrate. The laminated semiconductor structure includes a light absorbing layer that is disposed above the substrate and a plurality of window layers of a first conductivity type that are formed apart from each other on the light absorbing layer. Inside the laminated semiconductor structure, there is formed, for each window layer, a first of second conductivity type region that extends into the light absorbing layer from a surface of the window layer at an opposite side to the light absorbing layer. Inside the light absorbing layer, there is formed a second of second conductivity type region that is disposed such as to surround each of the plurality of window layers in plan view and extends from a surface of the light absorbing layer at an opposite side to the substrate toward a surface of the light absorbing layer at the substrate side.

Abstract: A gate driver includes a low-voltage circuit configured to be actuated by application of a first voltage and a high-voltage circuit configured to be actuated by application of a second voltage that is higher than the first voltage. The gate driver also includes a transformer and a capacitor connected in series to the transformer. The low-voltage circuit and the high-voltage circuit are connected by the transformer and the capacitor and configured to transmit a signal through the transformer and the capacitor.

Abstract: A semiconductor substrate (1) disclosed herein includes: an SiC single crystal substrate (10SB); a graphene layer (11GR) disposed on an Si plane of the SiC single crystal substrate (10SB); an SiC epitaxial growth layer (12RE) disposed above the SiC single crystal substrate (10SB) via the graphene layer (11GR); and a polycrystalline Si layer (15PS) disposed on an Si plane of the SiC epitaxial growth layer (12RE). The semiconductor substrate may include a graphite substrate or an silicon substrate disposed on a polycrystalline Si layer (15PS). The semiconductor substrate may further include an SiC polycrystalline growth layer (18PC) disposed on a C plane of the SiC epitaxial growth layer (12RE). Consequently, the present disclosure provides a low-cost and high-quality semiconductor substrate and a fabrication method thereof.

Abstract: A semiconductor substrate (1) according to an embodiment includes: a hexagonal SiC single crystal layer (13I); an SiC epitaxial growth layer (12E) disposed on an Si plane of an SiC single crystal layer (13I); and an SiC polycrystalline growth layer (18PC) disposed on a C plane opposite to the Si plane of the SiC single crystal layer (13I). The SiC single crystal layer (13I) includes a single crystal SiC thin layer (10HE) obtained by weakening the hydrogen ion implantation layer (10HI), and a phosphorus ion implantation layer (10PI). The phosphorus ion implantation layer (10PI) is disposed between the single crystal SiC thin layer (10HE) and the SiC polycrystalline growth layer (18PC). Consequently, the present disclosure provides a low-cost and high-quality semiconductor substrate and a fabrication method thereof.

Abstract: A semiconductor device includes a chip which has a first main surface on one side and a second main surface on the other side and which includes an active surface set at an inner portion of the first main surface and an outside surface set at a peripheral edge portion of the first main surface, a functional device which is formed at the active surface side, a projecting structure which includes an inorganic substance and projects at the outside surface side, and an organic film which covers the projecting structure.

Abstract: A semiconductor device of the present invention includes a gate electrode buried in a gate trench of a first conductivity-type semiconductor layer, a first conductivity-type source region, a second conductivity-type channel region, and a first conductivity-type drain region formed in the semiconductor layer, a second trench selectively formed in a source portion defined in a manner containing the source region in the surface of the semiconductor layer, a trench buried portion buried in the second trench, a second conductivity-type channel contact region selectively disposed at a position higher than that of a bottom portion of the second trench in the source portion, and electrically connected with the channel region, and a surface metal layer disposed on the source portion, and electrically connected to the source region and the channel contact region.

Abstract: A semiconductor device includes: a first transistor provided with an electron transit layer made of a nitride semiconductor, a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor that includes a second gate electrode, a second source electrode, and a second drain electrode. The first gate electrode and the second drain electrode are electrically connected to each other, while the first source electrode and the second source electrode are not electrically connected to each other.

Abstract: A semiconductor device includes a substrate having a main surface, a plurality of first wirings, each having a first embedded part embedded in the substrate and exposed from the main surface, and a mounted part which is in contact with the main surface and is connected to the first embedded part, a semiconductor element having an element rear surface and a plurality of electrodes bonded to the mounted parts, a plurality of second wirings, each having a second embedded part embedded in the substrate and exposed from the main surface and a columnar part protruding from the second embedded part in the thickness direction, and being located outward from the semiconductor element as viewed in the thickness direction; and a passive element located on the side facing the main surface in the thickness direction more than the semiconductor element, and electrically connected to the plurality of second wirings.

Abstract: A gate driver configured to apply a drive voltage signal to a gate of a switching element includes a low-voltage circuit chip and a high-voltage circuit chip. The low-voltage circuit chip includes a low-voltage circuit configured to be actuated by application of a first voltage. The high-voltage circuit chip includes a high-voltage circuit configured to be actuated by application of a second voltage that is higher than the first voltage. The gate driver further includes multiple transformer chips connected in series to each other. The low-voltage circuit chip and the high-voltage circuit chip are connected by the multiple transformer chips and configured to transmit a signal through the multiple transformer chips.

Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface, a unit cell including a diode region of a first conductivity type formed in a surface layer portion of the first surface of the semiconductor layer, a well region of a second conductivity type formed in the surface layer portion of the first surface of the semiconductor layer along a peripheral edge of the diode region, and a first conductivity type region formed in a surface layer portion of the well region, a gate electrode layer facing the well region and the first conductivity type region through a gate insulating layer and a first surface electrode covering the diode region and the first conductivity type region on the first surface of the semiconductor layer, and forming a Schottky junction with the diode region and an ohmic junction with the first conductivity type region.

Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.

Abstract: An electronic component includes a lower insulating layer, an upper insulating layer formed on the lower insulating layer, a first via electrode embedded in the lower insulating layer, a second via electrode embedded in the lower insulating layer at an interval from the first via electrode, and a resistance layer that is made of a metal thin film, is interposed in a region between the lower insulating layer and the upper insulating layer, and is electrically connected to the first via electrode and the second via electrode.

Abstract: Terahertz device includes first resin layer, columnar conductor, wiring layer, terahertz element, second resin layer, and external electrode. Resin layer includes first resin layer obverse face and first resin layer reverse face. Columnar conductor includes first conductor obverse face and first conductor reverse face, penetrating first resin layer in z-direction. Wiring layer spans between first resin layer obverse face and first conductor obverse face. Terahertz element includes element obverse face and element reverse face, and converts between terahertz wave and electric energy. Second resin layer includes second resin layer obverse face and second resin layer reverse face, and covers wiring layer and terahertz element. External electrode, disposed offset in a direction first resin layer reverse face faces with respect to first resin layer, is electrically connected to columnar conductor. Terahertz element is conductively bonded to wiring layer.

Abstract: A resistor includes a resistive element including a first surface and a second surface; a protective film having electrical insulating properties disposed on the first surface; and a pair of electrodes in contact with the resistive element. The protective film includes a first outer edge and a second outer edge. The resistive element includes a first slit and a second slit extending from the first surface through to the second surface and extending in the second direction. The first slit is located closest to the first outer edge; and the second slit is located closest to the second outer edge. As viewed in the thickness direction, a first distance from the first outer edge to the first slit and a second distance from the second outer edge to the second slit together have a length 15% or greater of a dimension of the protective film in the first direction.

Abstract: A resonant gate driver 200A includes an H-bridge circuit and a resonant inductor integrated on a semiconductor substrate. A first leg of the H-bridge circuit includes a first high-side transistor, a first output node, and a first low-side transistor such that they are arranged side-by-side in a first direction (x direction) in a first region defined along a first side. The second leg of the H-bridge circuit includes a second high-side transistor, a second output node, and a second low-side transistor such that they are arranged side-by-side in a first direction (x direction) in a second region defined along a second side. A resonant inductor is a parasitic inductance that occurs in a coupling means that electrically couples the first output node and the second output node.