Abstract: A semiconductor device includes an electron transit layer formed on first principal surface of the semiconductor layer, an electron supply layer formed on the electron transit layer, a gate conductive layer formed on the electron supply layer, a source conductive layer and a drain conductive layer that are formed on the electron supply layer such that the gate conductive layer is interposed between the source conductive layer and the drain conductive layer, an anode conductive layer that is formed on second principal surface of the semiconductor layer and that is electrically connected to the source conductive layer, a cathode conductive layer that is formed on the first principal surface of the semiconductor layer and that is electrically connected to the drain conductive layer, and a rectifying element formed by a part of the semiconductor layer such that the rectifying element is electrically connected to the anode and cathode conductive layers.

Abstract: A semiconductor substrate (1) includes: an SiC single crystal substrate (10SB), a first graphene layer (11GR1) disposed on an Si plane of the SiC single crystal substrate 10SB; an SiC epitaxial growth layer (12RE) formed above the SiC single crystal substrate via the first graphene layer; and a second graphene layer (11GR2) disposed on an Si plane of the SiC epitaxial growth layer. There is also included an SiC polycrystalline substrate (16P) provisionally bonded onto the SiC epitaxial growth layer via the second graphene layer. The SiC single crystal substrate is able to be reused by being separated from the SiC epitaxial growth layer. This semiconductor substrate further includes an SiC polycrystalline growth layer (18PC) CVD grown on the C plane of the SiC epitaxial growth layer; and the SiC epitaxial growth layer is transferred to the SiC polycrystalline growth layer.

Abstract: A thermal print head includes a heat-generating substrate, a resistor layer, a conductive layer, a first substrate, a second substrate, and a third substrate. The heat-generating substrate includes a heat-generating substrate obverse face and a heat-generating substrate reverse face that are spaced apart from each other in a thickness direction. The resistor layer is supported by the heat-generating substrate. The conductive layer is supported by the heat-generating substrate, and electrically connected to the resistor layer. The first substrate is located upstream of the heat-generating substrate in a sub-scanning direction. The second substrate is located upstream of the first substrate in the sub-scanning direction. The third substrate is bonded to the first substrate and the second substrate and higher in flexibility than the first substrate.

Abstract: A semiconductor light emitting device includes a semiconductor light source, a resin package surrounding the semiconductor light source, and a lead fixed to the resin package. The lead is provided with a die bonding pad for bonding the semiconductor light source, and with an exposed surface opposite to the die bonding pad The exposed surface is surrounded by the resin package in the in-plane direction of the exposed surface.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, amounting layer, switching elements, a moisture-resistant layer and a sealing resin. The substrate has a front surface facing in a thickness direction. The mounting layer is electrically conductive and disposed on the front surface. Each switching element includes an element front surface facing in the same direction in which the front surface faces along the thickness direction, a back surface facing in the opposite direction of the element front surface, and a side surface connected to the element front surface and the back surface. The switching elements are electrically bonded to the mounting layer with their back surfaces facing the front surface. The moisture-resistant layer covers at least one side surface. The sealing resin covers the switching elements and the moisture-resistant layer.

Abstract: A nitride semiconductor device includes an electron transit layer (103) that is formed of a nitride semiconductor, an electron supply layer (104) that is formed on the electron transit layer (103), that is formed of a nitride semiconductor whose composition is different from the electron transit layer (103) and that has a recess (109) which reaches the electron transit layer (103) from a surface, a thermal oxide film (111) that is formed on the surface of the electron transit layer (103) exposed within the recess (109), a gate insulating film (110) that is embedded within the recess (109) so as to be in contact with the thermal oxide film (111), a gate electrode (108) that is formed on the gate insulating film (110) and that is opposite to the electron transit layer (103) across the thermal oxide film (111) and the gate insulating film (110), and a source electrode (106) and a drain electrode (107) that are provided on the electron supply layer (104) at an interval such that the gate electrode (108) intervene

Abstract: A linear power supply circuit according to the present invention is provided with: an output transistor provided between an input end to which an input voltage is applied and an output end to which an output voltage is applied; and a driver for driving the output transistor on the basis of the difference between a voltage based on the output voltage and a reference voltage. The driver is provided with: a differential amplifier for outputting a voltage according to the difference between the voltage based on the output voltage and the reference voltage; a capacitor one end of which has an output of the differential amplifier applied thereto and the other end of which has the voltage based on the output voltage applied thereto; a converter for converting a voltage based on the output of the differential amplifier into an electrical current and outputting the electrical current; and an electrical current amplifier for amplifying the electrical current of the output of the converter.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

Abstract: A semiconductor device includes a semiconductor element, a first lead including a mounting portion for the semiconductor element and a first terminal portion connected to the mounting portion, and a sealing resin covering the semiconductor element and a portion of the first lead. The mounting portion has a mounting-portion front surface and a mounting-portion back surface opposite to each other in a thickness direction, with the semiconductor element mounted on the mounting-portion front surface. The sealing resin includes a resin front surface, a resin back surface and a resin side surface connecting the resin front surface and the resin back surface. The mounting-portion back surface of the first lead is flush with the resin back surface. The first terminal portion includes a first-terminal-portion back surface exposed from the resin back surface, in a manner such that the first-terminal-portion back surface extends to the resin side surface.

Abstract: Provided is a nitride semiconductor device 3 including a GaN electron transit layer 13, an AlGaN electron supply layer 14 in contact with the electron transit layer 13, a gate layer 15, formed selectively on the electron supply layer 14 and constituted of a nitride semiconductor composition effectively not containing an acceptor type impurity, and a gate electrode 16, formed on the gate layer 15, and satisfying the following formula (1): d g ? 2 ? E F ? q ? ( N DA + N A - N DD - N D ) ? 0 ? ? C + ? B - d B ? P ? 0 ? ? C > 0.

Abstract: A bridge circuit includes a high-side transistor connected between a power supply terminal and an output terminal, and a low-side transistor connected between the output terminal and a ground terminal. A high-side pre-driver and a low-side pre-driver drive the high-side transistor and the low-side transistor. A first transistor is connected between the output terminal and the ground terminal in a manner to form the regenerative path parallel to the low-side transistor. In a regenerative state in which a current sinks from the output terminal, a regenerative control circuit controls the voltage of a control terminal of the first transistor in a manner that an output voltage of the output terminal approaches a target voltage higher than the power supply voltage of the power supply terminal by a first voltage width.

Abstract: A chip resistor includes a resistor body, a first upper surface electrode, a second upper surface electrode, and an upper surface protection film on an upper surface of a substrate. The upper surface protection film covers the entire surface of the resistor body and the entire surface of the first upper surface electrode and the second upper surface electrode. The upper surface protection film includes a peripheral portion that is entirely in contact with the upper surface of the substrate.

Abstract: There is provided a semiconductor device that includes a wiring layer, a plurality of bonding layers arranged on the wiring layer and having conductivity, and a semiconductor element having a rear surface facing the wiring layer and a plurality of pads provided on the rear surface, and bonded to the wiring layer via the plurality of bonding layers, wherein the plurality of bonding layers are arranged in a grid shape when viewed along a thickness direction, wherein each of the plurality of pads is electrically connected to a circuit formed inside the semiconductor element and any of the plurality of bonding layers, and wherein at least one of the plurality of pads is located to be spaced apart from the plurality of bonding layers when viewed along the thickness direction.

Abstract: Disclosed is a chip component including a substrate having a first surface and a second surface on an opposite side from the first surface, and a third surface connecting the first surface and the second surface to each other, an external surface resin configured to cover at least the third surface of the substrate, and a terminal electrode formed on the first surface of the substrate and exposed from the external surface resin. A recessed portion is formed in an end portion of the third surface of the substrate, the end portion being on the first surface side. The external surface resin is embedded in the recessed portion.

Abstract: There is provided a semiconductor device that includes a wiring layer having a main surface and a rear surface which face opposite sides in a thickness direction, a first insulating layer covering an entirety of the rear surface, a second insulating layer which is in contact with the main surface, a semiconductor element which faces the second insulating layer and is mounted on the wiring layer, and a sealing resin which is in contact with the second insulating layer and covers the semiconductor element, wherein surface roughness of the main surface is larger than surface roughness of the rear surface.

Abstract: The present disclosure provides a power supply control device. The power supply control device includes a feedback voltage generator, an on-timing setting unit and an off-timing setting unit. The feedback voltage generator is configured to generate a feedback voltage by sampling a primary voltage of a transformer that forms an insulated switching power supply. The on-timing setting unit is configured to turn on a primary current of the transformer based on a comparison result between the feedback voltage and a slope-shaped reference voltage. The off-timing setting unit is configured to turn off the primary current after a predetermined on time has elapsed since the primary current was turned on. A sampling timing of the primary voltage is set based on an on timing of the primary current.

Abstract: An apparatus includes a control device configured to serve as a principal controlling agent in an electric power conversion device incorporating a switching circuit configured to be a bidirectional inverter. The control device is configured to subtract, from a reference signal that is determined in accordance with an operation mode of the electric power conversion device, a multiplied signal obtained by multiplying a control-target current of the switching circuit by a prescribed coefficient to generate, based on a result of the subtraction, a control signal for controlling the bidirectional inverter.

Abstract: This light-emitting element drive control device (100) comprises: a drive logic unit (113) which performs a drive control of a switch output stage (N1, D1, L1) for dropping an input voltage (VIN) to an output voltage (VOUT) and supplying a light-emitting element therewith: a charge-pump power supply unit (?) which generates a step-up voltage (CP) higher than the input voltage (VIN); and a current detecting comparator (114) which receives a supply of the step-up voltage (CP) and the output voltage (VOUT) as power supply voltages, and generates control signals (SET, RST) for the drive logic unit (113) by directly comparing a current detection signal (Vsns) corresponding to an inductor current (IL) of the switch output stage with a peak detection value (Vsns_pk) and a bottom detection value (Vsns_bt).

Abstract: A semiconductor device includes first and second insulated-gate transistors in parallel with each other, a charger-discharger, and a gate voltage correction circuit. The charger-discharger can perform first control to charge both of the gates of the first and second transistors, second control to discharge both of the gates of the first and second transistors, and third control to charge one of the gates of the first and second transistors. The gate voltage correction circuit corrects the gate voltages of the first and second transistors to eliminate the difference between those voltages in at least one of the first control, the second control, and protection operation in which the first and second transistors are forcibly kept off.