Abstract: A semiconductor device includes: a semiconductor chip including a main surface electrode; a first mounting lead; a second mounting lead; a connection lead which overlaps with the main surface electrode, the first mounting lead and the second mounting lead when viewed in a thickness direction of the semiconductor chip and makes electrical conduction between the main surface electrode, the first mounting lead and the second mounting lead; and a resin portion which covers the semiconductor chip, the first mounting lead and the second mounting lead, wherein the resin portion has a resin bottom lying on the same plane as a bottom of the first mounting lead and a bottom of the second mounting lead.

Abstract: A semiconductor device includes an n-type drain layer, an n-type base layer provided on the n-type drain layer, a p-type base layer and an n-type source layer partially formed in surface layer portions of the n-type base layer and the p-type base layer, respectively, a gate insulation film formed on a surface of the p-type base layer between the n-type source layer and the n-type base layer, a gate electrode formed on the gate insulation film facing the p-type base layer across the gate insulation film, a p-type column layer formed within the n-type base layer to extend from the p-type base layer toward the n-type drain layer, a depletion layer alleviation region arranged between the p-type column layer and the n-type drain layer and including first baryons converted to donors, a source electrode connected to the n-type source layer, and a drain electrode connected to the n-type drain layer.

Abstract: A semiconductor device includes a plurality of die pad sections, a plurality of semiconductor chips, each of which is arranged in each of the die pad sections, a resin encapsulation portion having a recess portion for exposing at least a portion of the die pad sections, the resin encapsulation portion configured to cover the die pad sections and the semiconductor chips, and a heat radiation layer arranged in the recess portion. The heat radiation layer includes an elastic layer exposed toward a direction in which the recess portion is opened. The heat radiation layer directly faces at least a portion of the die pad sections. The elastic layer overlaps with at least a portion of the die pad sections when seen in a thickness direction of the heat radiation layer.

Abstract: A semiconductor light emitting device includes a semiconductor light source, a resin package surrounding the semiconductor light source, and a lead fixed to the resin package. The lead is provided with a die bonding pad for bonding the semiconductor light source, and with an exposed surface opposite to the die bonding pad The exposed surface is surrounded by the resin package in the in-plane direction of the exposed surface.

Abstract: A light emitter driving device has a decoder portion which monitors a rectified voltage and generates a dimming signal, and a drive current control portion which controls a drive current to a light emitter according to the dimming signal. The decoder portion has a comparator which compares the rectified voltage with a predetermined threshold voltage to generate a comparison signal, a sampling counter which measures high-level and low-level periods of the comparison signal, a duty calculation portion which calculates the duty of the rectified voltage based on the output of the sampling counter, a filter calculation portion which excludes sporadic variation in duty by applying digital filtering to the output of the duty calculation portion, and a dimming signal generation portion which generates the dimming signal based on the output of the filter calculation portion.

Abstract: A semiconductor laser device includes an n-type clad layer, a first p-type clad layer and a ridge stripe. The device also includes an active layer interposed between the n-type clad layer and the first p-type clad layer, and a current-blocking layer formed on side surfaces of the ridge stripe. The ridge stripe of the device includes a second p-type clad layer formed into a ridge stripe shape on the opposite surface of the first p-type clad layer from the n-type clad layer. The ridge stripe is formed such that a first ridge width as the width of a surface of the second p-type clad layer exists on the same side as the first p-type clad layer and a second ridge width as the width of a surface of the second p-type clad layer exists on the opposite side from the first p-type clad layer.

Abstract: A semiconductor device is formed, the semiconductor device including: an SOI substrate; field insulating films that are formed on the SOI substrate and that separate a plurality of element formation regions; first and second HV pMOSs, and first and second LV pMOSs that are formed in the plurality of element formation regions; a first interlayer insulating film and a second interlayer insulating film formed on the SOI substrate; a mold resin formed on the second interlayer insulating film; and conductive films that are formed on the first interlayer insulating film and that are interposed between the plurality of element formation regions, and the field insulating films and mold resin.

Abstract: Disclosed herein is a block copolymer comprising a first segment and a second segment that are covalently bonded to each other and that are chemically different from each other; where the first segment has a first surface free energy and where the second segment has a second surface free energy; and an additive copolymer; where the additive copolymer comprises a surface free energy reducing moiety where the surface free energy reducing moiety has a lower surface free energy than that of the first segment and the second segment; the additive copolymer further comprising one or more moieties having an affinity to the block copolymer; where the surface free energy reducing moiety is chemically different from the first segment and from the second segment; where the additive copolymer is not water miscible; and where the additive copolymer is not covalently bonded with the block copolymer.

Abstract: Disclosed herein is a method comprising disposing a first composition comprising a first block copolymer upon a substrate; where the first block copolymer comprises a first segment and a second segment that are covalently bonded to each other and that are chemically different from each other; where the first segment has a first surface free energy and where the second segment has a second surface free energy; and disposing a second composition comprising an second copolymer upon a free surface of the first block copolymer; where the second copolymer comprises a surface free energy reducing moiety; where the surface free energy reducing moiety has a lower surface free energy than the first surface free energy and the second surface free energy; the second copolymer further comprising one or more moieties having an affinity to the first block copolymer; where the surface free energy reducing moiety is chemically different from the first segment and from the second segment.

Abstract: A lighting device includes a substrate and a planar light source portion including a plurality of LED chips arrayed on the substrate. The planar light source portion faces an illumination space (space to be illuminated) by a predetermined opening area. The plurality of LED chips are arrayed on the substrate such that the mounting density with respect to the opening area is not less than 3/cm2, and accordingly, a planar light source is formed.

Abstract: A mobile telephone includes a cartilage conduction unit for making contact with the ear cartilage. The cartilage conduction unit is provided to at least one of two corner parts at an upper side of the mobile telephone. The mobile telephone can include a surface of an outer wall and a cartilage conduction vibration source arranged inward from the surface of the outer wall, the vibration of the cartilage conduction vibration source being transmitted to the surface of the outer wall, wherein when the surface of the outer wall is brought into contact with at least a part of the ear cartilage around the entrance part to the external auditory meatus without making contact with the auricular helix, the sound pressure inside the external auditory meatus at about 1 cm from the entrance part of the external auditory meatus has an at least 10 dB increase compared to the non-contact state.

Abstract: [Subject] To provide a highly-reliable and small-size chip component, e.g., a chip resistor having an accurate resistance value. [Solution] The chip resistor (10) includes: a substrate (11); a plurality of resistor elements each having a resistive film portion (20) provided on the substrate (11) and an aluminum-containing interconnection film portion (21) provided in contact with the resistive film portion (20); electrodes (12, 13) provided on the substrate (11); and a plurality of fuses (F) each having an aluminum-containing interconnection film portion integral with the aluminum-containing interconnection film portion of the resistor element and disconnectably connecting the resistor element to the electrodes (12, 13). [Effect] The resistance of the chip resistor can be adjusted at a desired resistance value by selectively disconnecting desired ones of the fuses.

Abstract: A chip resistor with a reduced thickness is provided. The chip resistor includes an insulating substrate, a resistor embedded in the substrate, a first electrode electrically connected to the resistor, and a second electrode electrically connected to the resistor. The first electrode and the second electrode are spaced apart from each other in a lateral direction that is perpendicular to the thickness direction of the substrate.

Abstract: A switching regulator has an output stage which, with an output switch element, an inductor, a rectifying element, and a smoothing element, generates an output voltage from an input voltage, a divided voltage generator which generates a divided voltage from a switch voltage generated at one terminal of the rectifying element, a selector which outputs one of the divided voltage and a fixed voltage in accordance with a switching signal as a select voltage, a zero-cross comparator which monitors the select voltage to generate a zero-cross detection signal, and a controller which generates the switching signal in accordance with the necessity of monitoring the zero-cross of an inductor current and which performs on/off control of the output switch element reflecting the zero-cross detection signal.

Abstract: The present invention relates to barrier layer compositions that are applied above a photoresist composition for immersion lithography processing. In a further aspect, new methods are provided for immersion lithography processing.

Abstract: A terminal device has: a sensor unit which perform a measurement; a position detection unit which acquires information for specifying a position; a timing unit which acquires time information; a communication unit which communicates via a communication network; and a control unit. The control unit generates position information for indicating a position of the terminal device by the position detection unit. Besides, the control unit changes accuracy of the position information within a predetermined range, and generates information for transmission related with the changed position information, the time information gotten by the timing unit, and measurement information indicating a measurement result of the sensor unit. In addition, the control unit controls the communication unit so as to transmit the information for the transmission to an information processing device via a communication network.

Abstract: The present invention relates to a composition comprising a stable aqueous dispersion of polymer particles, an oxidoreductase, and a cofactor for the oxidoreductase and a method for its preparation. The invention is useful for converting certain classes of VOCs to non-VOCs.

Abstract: To assign angle-dependent information to an input image in order to highlight and display one-dimensional patterns. First, data of an input image is inputted to a computer (Sa1). An arbitrarily defined constant m is then inputted as a contrast intensity (Sa2). Next, a closed region (x, y) made up of a plurality of pixels in the input image is demarcated as a target region D, degrees of inclination between respective two pixels, namely, a pixel of interest in the target region D and arbitrarily defined neighboring pixels thereof, are summed over a whole circumference around the pixel of interest, and the sum is divided by the number of pixels within the target region to calculate a mean value thereof (Sa3). Furthermore, an amplitude value ? of a gradient obtained in step (Sa3) is multiplied by the contrast intensity m (where m is a positive constant) inputted in step (Sa2) and an arbitrarily defined offset value ? is added to the obtained value (Sa4) to obtain a final output image (Sa5).

Abstract: The present invention improves the efficiency of a switching power supply in a light load. A control circuit is configured to repeat a driving duration enabling the switching element to be switched and a stop duration stopping the switching in a light load state. A pulse signal generating portion generates a driving pulse signal, in which the driving pulse signal at least includes a pulse in the driving duration, and the lighter a load is, the less the number of pulses in the driving duration is. A first driver drives a first switching transistor according to the at least one pulse in the driving pulse signal other than predetermined K pulses (K is a natural number). The K pulses are in the driving pulse signal when the number of the pulses is reduced to K.

Abstract: The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.