Abstract: A semiconductor memory device with a built-in self test circuit includes a semiconductor substrate, a memory cell array formed on the semiconductor substrate, an input buffer provided on the semiconductor substrate to receive externally applied data, a test circuit coupled to the memory cell array and the input buffer on the semiconductor substrate to store a program received through the input buffer to generate test data of the memory cell array according to the stored program to carry out testing of the memory cell array, and a select circuit selectively applying to the memory cell array test data applied from the test circuit and data applied from the input buffer depending upon a test operation and a normal operation.

Abstract: A jitter measurement circuit includes: a conversion section sampling one of a reference signal and a measurement target signal in response to the other of the signals, thereby obtaining a sampling data string; and a determination section measuring jitter of the measurement target signal on the basis of the sampling data string obtained by the conversion section. Since the reference signal is a stable signal having a predetermined cycle, the sampling data string as a measurement result depends on the measurement target signal. Therefore, it is possible to simply measure jitter level in accordance with irregularity of the measurement result and on the basis of relative measurement to expected value data.

Abstract: A power module includes a first substrate with a power semiconductor device mounted thereon, a second substrate with a control circuit for controlling the power semiconductor device formed thereon, a smoothing capacitor electrically connected to the power semiconductor device for smoothing a voltage to be externally supplied to the power semiconductor device, and a case including a case frame and a case lid. The case has an interior in which the first substrate, the second substrate and the smoothing capacitor are disposed, and the smoothing capacitor is disposed in contact with a side surface of the case frame.

Abstract: A semiconductor device having a structure in which no short circuit occurs between plug interconnections even when a void occurs in an insulating layer in a gap between wiring layers and a method of manufacturing the same are attained. The method includes: a step of forming transfer gates so as to be close to each other with a gap on a semiconductor substrate; a step of burying the gap and covering a wiring layer; a step of opening a contact hole in an insulating layer in the gap portion; a step of depositing a short-circuit preventing insulating film in the contact hole; an etch back step of removing the short-circuit preventing insulating film at least on the bottom of the gap to expose the semiconductor substrate; and a step of forming a plug interconnection.

Abstract: A semiconductor manufacturing method is mainly contemplated, improved to prevent an altered surface layer of a resist from being removed when a single patterned resist is used to provide dry-etch and wet-etch successively. On a semiconductor substrate an insulation film and a conductive layer are formed successively. On the conductive layer a patterned resist is formed. With the patterned resist used as a mask, the conductive layer is dry-etched. A surface layer of the patterned resist is partially removed. With the patterned resist used as a mask, the insulation film is wet-etched.

Abstract: The substrate carrier management system includes a pre-diffusion processing apparatus, a carrier cleaner, and a carrier conveyer. The pre-diffusion processing apparatus unloads a substrate from a supplied carrier in which the substrate is stored, performs predetermined processing on the substrate, and transfers the processed substrate stored in a carrier to be used after processing. The carrier cleaner cleans a carrier emptied as a result of taking a substrate out of the carrier. The carrier conveyer conveys a carrier between the pre-diffusion processing apparatus and the carrier cleaner. The empty carrier unloaded from the pre-diffusion processing apparatus is cleaned by the carrier cleaner, and the processed substrate is stored in the empty carrier. With this arrangement, it is possible to automatically change carriers and thereby continuously use a cleaned carrier in the subsequent step without using a dedicated carrier.

Abstract: An uppermost interlayer isolation film is provided on a semiconductor substrate. An uppermost wire is provided on the uppermost interlayer isolation film. A silicon oxide film is provided to cover the upper surface and the side wall of the uppermost wire. A nitride film is provided on the uppermost interlayer isolation film to cover the uppermost wire through the silicon oxide film. A polyimide film is provided on the nitride film. A portion of the uppermost interlayer isolation film other than a portion located under the uppermost wire is downwardly scooped. The nitride film covers the scooped portion of the uppermost interlayer isolation film. According to the present invention, a semiconductor device improved to be capable of improving coverage of a silicon nitride passivation film is obtained.

Abstract: In a capacitor formation area A1, a capacitor C1 is formed. The capacitor is constituted by a lower-layer electrode-use polysilicon layer 105 (lower-layer electrode) formed on a LOCOS separation film 101, a nitride film 106 (dielectric film) and an upper-layer electrode-use polysilicon layer 107 (upper-layer electrode). In this case, the lower-layer electrode-use polysilicon layer 105 and the nitride film 106 are formed as the same plane pattern. In CMOS formation area A2, an NMOS transistor Q11 is formed on a P-well region 102 and a PMOS transistor Q12 is formed in an N-well region 103. Both of the gate electrodes of NMOS transistor Q11 and NMOS transistor Q21 are formed by the upper-layer electrode-use polysilicon layer 107.

Abstract: A test pattern generation circuit for use with a self-diagnostic circuit which produces a test pattern through use of a microinstruction code, which includes a memory device RAM/ROM which temporarily stores the microinstruction code and outputs two different instruction codes within one clock cycle; a selector SEL which receives output from the memory device and selectively delays the two instruction codes, thereby outputting one code; and a pattern generation circuit PG which produces a test pattern corresponding to output from the selector.

Abstract: A process control device controls a plurality of processing devices placed in parallel to perform at least two process steps for consecutively processing workpieces in a lot. The process control device includes a device group information for grouping of a plurality of processing devices into a plurality of device groups. For example, when the workpieces are semiconductor devices, processing devices having identical deviating characteristics are grouped into the same group to perform a plurality of photolithographic steps. The process control device further includes a device group selecting unit for selecting the device group such that the lot is processed in the second process step using a processing device included in the same device group as a processing device used in the first process step.

Abstract: A power module includes a substrate with a power semiconductor device mounted thereon, a case having an interior in which the substrate is disposed, a cooling fin having a surface on which the substrate and the case are placed, and a smoothing capacitor disposed on an opposite surface of the cooling fin from the surface on which the substrate is placed, the smoothing capacitor being electrically connected to the power semiconductor device for smoothing a voltage to be externally supplied to the power semiconductor device.

Abstract: A substrate testing apparatus includes a first rail group made of a plurality of rails disposed in parallel with each other, a second rail group made of a plurality of rails disposed in parallel with each other in a direction that crosses the first rail group, a plurality of probe units disposed to cover respective intersections of the rails included in the first rail group and the rails included in the second rail group and being movable along the rails included in the first rail group and the second rail group, and corresponding interval maintaining means for keeping each rail included in the first rail group at an interval corresponding to an arrangement of locations to be measured on a substrate subjected to measurement, wherein the plurality of probe units each include a probing needle to be brought into contact with a surface of the substrate.

Abstract: An interbay transportation system includes bays in which process equipment are provided, stockers provided for the individual bays, and a vehicle traveling through the stockers for transporting a semi-processed product from one of the stockers to another. Timing to start transportation is determined according to the operation status of the process equipment and the number of semi-processed products in the stocker.

Abstract: A barrier metal layer constituted of a TiN layer and a Ti layer is formed on a surface of an interlayer insulating film and on an inside surface of an interconnection recess formed in the interlayer insulating film while a substrate is maintained at a temperature of at least 200° C. and lower than 300° C. The interconnection recess is filled with a conductive layer and an extra part of the conductive layer that is deposited on the interlayer insulating film is removed through such a polishing process to form a conductive plug. In the process of forming the barrier metal layer, as the substrate is maintained at the temperature, the residual stress in the deposited barrier metal layer can be reduced. Accordingly, it is achieved to suppress peeling which occurs at the interface between the barrier metal layer and the interlayer insulating film in the polishing process.

Abstract: In each of a plurality of memory chips in the semiconductor integrated circuit device, an address signal of a defective memory cell in a memory circuit is obtained by a pattern generation tester circuit and a repair analysis circuit, and stored in a replacement storage circuit. The address signal read out of the replacement storage circuit is set to a replacement-repair circuit, and the defective memory cell is replaced with a spare memory cell. The replacement of a defective memory cell with a spare memory cell is allowed even after packaging, so that the yield is increased. The test time is also reduced, as the plurality of memory chips are tested in parallel.

Abstract: A conveyance system which performs conveying action operating carrier vehicles, including a loop track, carrier vehicles which run on the track, a station where each carrier vehicle performs loading and unloading of a cargo, and a standby station for storing the carrier vehicles in a standby state. The number of the carrier vehicles to be used is determined from a conveyance command number, and can be automatically determined in correspondence with the load in the conveyance system. Accordingly, even if the load is not uniform but significantly varied, the conveying action can be conducted readily and efficiently.

Abstract: A trench is formed by performing an anisotropic etching treatment on a silicon substrate with the use of a mask pattern including a pad oxide film, a polysilicon film, and a silicon nitride film formed on the silicon substrate, as a mask. Next, the side surface of the polysilicon film is retreated by etching so that the part of an oxide film formed on the side surface of the polysilicon film may not be hung over the part of an oxide film formed on the side surface of the pad oxide film. Next, an oxide film is formed by performing a thermal oxidation treatment on the inner wall surface of the trench including the exposed side surface of the polysilicon film. This produces a semiconductor device that prevents voids from being formed in a trench isolation structure.

Abstract: There is provided an apparatus and method of testing a semiconductor integrated circuit, which apparatus and method enable testing of various semiconductor integrated circuits having different characteristics, fulfillment of the function of generating DAC data, and adaptation of various analog characteristic tests. An input range of a BOST device is switchable in accordance with the level of a DAC of a DUT, so that the test apparatus can handle DUTs of different types having different analog output levels.

Abstract: A semiconductor module that comprises a plurality of semiconductor chips mounted on a single substrate and which readily diagnoses all the semiconductor chips. A plurality of semiconductor chips are mounted on a single substrate. The semiconductor module is provided with a mode signal pin for receiving a mode signal for requesting performance of a diagnostic operation, as well as with a result output pin for outputting diagnostic results. Further, each of the semiconductor chips is provided with a diagnostic circuit for diagnosing the status of the corresponding semiconductor chip. The semiconductor module is also provided with a diagnosis controller for controlling the diagnostic circuits such that all the semiconductor chips are diagnosed in parallel or serially after a mode signal for requesting a diagnostic operation has been supplied to the mode signal pin.

Abstract: A method for preparing a manufacturing plan for a manufacturing factory having multiple equipments and charged with multiple processes. The equipment is assigned to the processes to determine an operation pattern for a day. A load of each process is allotted among the equipment assigned to the process. Total load of each equipment is calculated by summing the allotted load. A capability index of each equipment is determined by dividing capacity of the equipment by the total load of the equipment. The capability index is multiplied by the allotted load to provide a feasible load of the equipment for the process. By summing the feasible load of each equipment, a total feasible load under the operation pattern is calculated for each process. By comparing the total feasible load with the load for each process, the operation pattern is determined whether acceptable or not.