Abstract: A memory tester including an algorithmic pattern generator (ALPG) for generating a test pattern as a digital signal based on vector data is provided with a digital-to-analog converter built in the memory tester or provided outside the memory tester. Thus, the function of a device under test (DUT) having the analog-to-digital converting function can be verified. In other words, an address signal included in the test pattern generated in the ALPG is used for generating an analog signal to be input to the DUT having the analog-to-digital converting function, not for address designation. A control unit compares an output digital signal generated in the DUT with the address signal generated in the ALPG as a test digital signal to detect the degree of agreement between these signals, thereby verifying the analog-to-digital converting function of the DUT.

Abstract: A process control device includes: a change table detection unit to determine existence of a change table corresponding to a progress file; a progress file adjustment unit to change, when the change table detection unit determines that there exists a change table, the content of the progress file based on the change table; a unit to control a transport device of an item in process based on the progress file changed by the progress file adjustment unit; and a unit to control a manufacturing device of the item based on the progress file changed by the progress file adjustment unit. The manufacturing device control unit controls the manufacturing device based on the progress file that has been changed by the progress file adjustment unit, and thus, it is possible to change the processing orders, processing conditions and the like even when individual items are in respective manufacturing steps.

Abstract: An improved etching method allowing the formation of a silicon nitride film with an adequate film thickness at the sidewall portion of a pattern is disclosed. A silicon nitride film formed to cover a stepped pattern is dry-etched, employing plasma of mixed gases containing CH2F2 and O2. As a result, a sidewall spacer of the silicon nitride film is formed at the sidewall of the pattern in a self-aligned manner.

Abstract: A process control device for controlling a processing device and a transport apparatus while updating process information of a lot includes: a control information update unit to update control information for controlling the processing device and the transport apparatus; a work-in-process information update unit to update the work-in-process information indicating a location of a lot; a processing device control unit to control the processing device according to the control information updated by the control information update unit and the work-in-process information updated by the work-in-process information updated unit; and a transport apparatus control unit to control the transport apparatus according to the control information updated by the control information update unit and the work-in-process information updated by the work-in-process information update unit.

Abstract: An external test ancillary device (BOST device) analyzes measured information output from a semiconductor integrated circuit and transmits a result of analysis to a semiconductor test apparatus. The external test ancillary device includes a DAC counter for generating input data; a digital-to-analog converter for converting the data output from the counter from a digital signal into an analog signal; an analog-to-digital converter which receives data output from the digital-to-analog converter by way of a loopback line and converts the data from an analog signal into a digital signal; a DSP analysis section for performing self-diagnostic operation on the basis of data output from the analog-to-digital converter; measured data memory, an address counter, and a data write control circuit.

Abstract: A hard mask insulating layer is formed on a gate electrode which is formed on a main surface of a silicon substrate with a gate insulating layer interposed. An SiN sidewall spacer is directly formed on a thin SiO2 layer which is formed to cover a side surface of the gate electrode. A contact hole is formed to penetrate an interlayer insulating layer formed on an SiN stopper layer and reach the main surface of the silicon substrate.

Abstract: There are provided a test apparatus and a test method for testing a semiconductor integrated circuit which facilitate control of a BOST device and improve the versatility of the BOST device. There is provided an interface for exchanging signals between a BOST device and an external controller. A test control signal and a test result analysis signal are exchanged by means of the interface, thus effecting a test and analysis of the test.

Abstract: Providing an acceleration sensor in which a base portion and a cap portion are bonded to each other and a sensor portion is sealed off between these two, and which has an improved bonding strength between the base portion and the cap portion. A sensor portion and a frame portion surrounding a periphery of the sensor portion are disposed on a semiconductor substrate. A base portion is comprised, where a diffusion preventing layer and a non-doped polycrystalline silicon layer are stacked one atop the other on the frame portion. A cap portion is comprised, where a nickel layer is formed on a base unit. The non-doped polycrystalline silicon layer of the base portion and the nickel layer of the cap portion are bonded to each other by eutectic bonding.

Abstract: A semiconductor test apparatus includes an analog-to-digital converter for converting into a digital signal an analog output from a circuit under test; a test-apparatus-ADC-control-signal generation circuit for generating a control signal for the analog-to-digital converter in accordance with an activation signal entered from the outside; a measured data memory for storing, as measured data for each conversion, a signal output from the analog-to-digital converter; an address counter for generating an address signal for the measured data memory; a DAC counter for generating data to be input to the circuit under test; and a data write control circuit which produces, in response to a flag signal output from the analog-to-digital converter and representing that conversion is being performed, an update signal for the address counter, a memory write signal for the measured data memory, and an update signal for the DAC counter.

Abstract: An external test ancillary device (BOST device) analyzes measured information output from a semiconductor integrated circuit and transmits a result of analysis to a semiconductor test apparatus. The external test ancillary device includes a DAC counter for generating input data; a digital-to-analog converter for converting the data output from the counter from a digital signal into an analog signal; an analog-to-digital converter which receives data output from the digital-to-analog converter by way of a loopback line and converts the data from an analog signal into a digital signal; a DSP analysis section for performing self-diagnostic operation on the basis of data output from the analog-to-digital converter; measured data memory, an address counter, and a data write control circuit.

Abstract: A structure of a BiCMOS transistor hindering over-etching of source/drain regions of a MOS transistor and a manufacturing method thereof are provided. A polysilicon film that is to be a gate electrode lower layer of a MOS transistor is formed, and thereon, another polysilicon film that is to be a gate electrode upper layer of the MOS transistor as well as to be a base electrode of a bipolar transistor is formed. Thereafter, etching is conducted to form the polysilicon film to be the base electrode of the bipolar transistor and the gate electrode at the same time. Here, an oxide film shown in FIG. 4 serves as a protective film, thereby hindering over-etching of n type and p type wells to be active regions of respective MOS transistors.

Abstract: A semiconductor device having a structure in which no short circuit occurs between plug interconnections even when a void occurs in an insulating layer in a gap between wiring layers and a method of manufacturing the same are attained. The method includes: a step of forming transfer gates so as to be close to each other with a gap on a semiconductor substrate; a step of burying the gap and covering a wiring layer; a step of opening a contact hole in an insulating layer in the gap portion; a step of depositing a short-circuit preventing insulating film in the contact hole; an etch back step of removing the short-circuit preventing insulating film at least on the bottom of the gap to expose the semiconductor substrate; and a step of forming a plug interconnection.

Abstract: A trench is formed by performing an anisotropic etching treatment on a silicon substrate with the use of a mask pattern including a pad oxide film, a polysilicon film, and a silicon nitride film formed on the silicon substrate, as a mask. Next, the side surface of the polysilicon film is retreated by etching so that the part of an oxide film formed on the side surface of the polysilicon film may not be hung over the part of an oxide film formed on the side surface of the pad oxide film. Next, an oxide film is formed by performing a thermal oxidation treatment on the inner wall surface of the trench including the exposed side surface of the polysilicon film. This produces a semiconductor device that prevents voids from being formed in a trench isolation structure.

Abstract: A semiconductor device testing method is disclosed which comprises a first process 39, a second process 41 and a third process 43. In the first process 39, a test function part of a semiconductor device having a built-in self-test function is subjected to a self-diagnostic test, and a main circuit part of the device in question is tested by its test function part. If the result of either of the two tests on the device turns out to be abnormal, the device in question is rejected as defective. The test results are saved. In the second process 41, the main circuit part of each semiconductor device rejected as defective in the first process 39 is tested by use of an external test signal. If the result of the test on the semiconductor device judged faulty in the first process 39 turns out to be normal in the second process 41, then the device in question is judged normal in the third process 43.

Abstract: A semiconductor manufacturing system having a high processing efficiency and a high product output includes a processing device for simultaneously processing a prescribed number of lots for which it is reserved, and a semiconductor manufacturing system control device connected to the processing device for managing the manufacturing steps.

Abstract: The object of the invention is to improve a characteristic under a reverse bias. A P base layer (6) is provided as a plurality of band-shaped portions parallel with each other. A P+ base layer to be a downward protrusion having a high impurity concentration is not formed in a bottom portion of the P base layer (6). The P base layer (6) is formed more shallowly than an N layer (17), and furthermore, the band-shaped portions forming the P base layer (6) are coupled to each other at ends thereof. Moreover, an N source layer (5) is ladder-shaped and is connected to a source electrode (16) through only a crosspiece portion thereof.

Abstract: A barrier layer is formed at a bottom portion, for example, of a through hole. The thickness of the barrier layer at an upper area, for example, of the through hole is made uniform. The method of manufacturing a semiconductor device includes the steps of: forming a barrier layer by sputtering on a main surface of a silicon substrate while maintaining a first distance between a main surface of the target and the main surface of the silicon substrate; and forming a titanium nitride layer by sputtering on and adjacent to a titanium nitride layer by scattering a target material while maintaining a second distance longer than the first distance between the main surface of the target and the main surface of the silicon substrate.

Abstract: In a method of manufacturing a semiconductor device, a first resist pattern, which evolves an acid, is formed on a semiconductor substrate. The first resist pattern is treated with a chemical solution containing a crosslinking agent and a swelling promoter. The crosslinking agent is capable to bring about crosslinking in the presence of an acid at the surface layer of the first resist pattern. The crosslinking agent and swelling promoter in the chemical solution permeate into the surface layer of the first resist pattern, thereby swells the surface layer. The chemical solution is removed from the surface of the first resist pattern. The first resist pattern is caused to evolve an acid, by which a crosslinked film is formed in the swollen surface layer of the first resist pattern. Thus, a second resist pattern is formed, and the semiconductor substrate is etched through the second resist pattern as a mask.

Abstract: A repair analysis circuit for redundancy, a redundant method for repairing a redundant, and a semiconductor device that can shorten time for testing defective memory cells, that eliminate the need of failure memories having a huge capacity for storing defective bits to make the testing apparatus inexpensive, and that easily cope with increase and decrease in IO numbers. A large number of IO outputs MOUT are collectively compared with a specified expected value, and as a result resultant judgment information DOUT is outputted to an error information acquiring device 22, and an analyzing device 23 reads table information sequentially from each block to obtain replacing data, and the replacing data are outputted serially to the external tester through the external I/F circuit 24. The redundant memory cell 4a itself can be made to compare with a specified expected value in the same manner as other memory cells 4 or the like.

Abstract: A corrected irradiation region (14) to be irradiated with a laser light under given output conditions to remove an opaque extension defect (13) is set to include: {circumflex over (1)} an irradiation region (14A) containing the opaque extension defect (13) and having widths w1 and w2 and {circumflex over (2)} a pattern repaired region (14B) having the width w2 and extending in the negative direction in a first direction D1 by the absolute value of a quantity of bias offset of repairing &Dgr;w from the connection between the opaque extension defect (13) and the pattern edge (12E). The quantity of correction offset &Dgr;w is set so that the dimensional variation rate of the resist pattern transferred falls within a range permitted for the device quality. Part of the pattern edge (12E) is missing by the width |&Dgr;w| after the irradiation of laser light.