Abstract: A first resist layer, capable of generating an acid, is formed on a semiconductor base layer and is developed in a shortened developing time than usual. The first resist pattern is covered with a second resist layer containing a material capable of crosslinkage in the presence of an acid. The acid is generated in the first resist pattern by application of heat or by exposure to light, and a crosslinked layer is formed in the second resist pattern at the interface with the first resist pattern as a cover layer for the first resist pattern, thereby the first resist pattern is caused to be thickened. The non linked portion of the second resist layer is removed and the fine resist pattern is formed. Thus, the hole diameter of the resist pattern can be reduced, or the isolation width of a resist pattern can be reduced.

Abstract: A method of process control includes the steps of preparing recycling procedure data for each type of film formed on a wafer by diffusion processing, setting a recycle control number for controlling recycling processing based on the recycling procedure data, and outputting a recycling instruction to the recycling apparatus when the prescribed number of non-product wafers are accumulated and when an accept request is received from the recycling apparatus.

Abstract: A semiconductor test apparatus and method for performing a test on a nonvolatile semiconductor memory such as a flash memory while preventing excessive erasing with reliability. In each erase operation, all addresses are scanned to fetch an error address and error data into a catch memory. Then, on the basis of error information (error address and error data), a rewrite operation is performed to write data on all memory cells. The write data varies according to a comparison result between an address signal and an error address signal. If they disagree, a “0” is written on a memory cell at the address. If they agree, a “0” is written on a “pass” memory cell and a “1” is virtually written on a fail memory cell.

Abstract: A replacement information storage unit stores additional replacement information determined according to testing carried out during or after assembly. A replacement information addition load unit receives additional replacement information from outside a plurality of memory chips. A replacement data retain unit stores address information corresponding to a defective memory cell found during a fabrication process of a memory chip, and can alter the output address signal according to externally applied additional replacement information.

Abstract: An interbay transportation system includes bays in which process equipment are provided, stockers provided for the individual bays, and a vehicle traveling through the stockers for transporting a semi-processed product from one of the stockers to another. Timing to start transportation is determined according to the operation status of the process equipment and the number of semi-processed products in the stocker.

Abstract: In each of a plurality of memory chips in the semiconductor integrated circuit device, an address signal of a defective memory cell in a memory circuit is obtained by a pattern generation tester circuit and a repair analysis circuit, and stored in a replacement storage circuit. The address signal read out of the replacement storage circuit is set to a replacement-repair circuit, and the defective memory cell is replaced with a spare memory cell. The replacement of a defective memory cell with a spare memory cell is allowed even after packaging, so that the yield is increased. The test time is also reduced, as the plurality of memory chips are tested in parallel.

Abstract: A dielectric layer for capacitive element is formed on a lower electrode. An interlayer insulating layer is formed on the lower electrode and the dielectric layer for capacitive element. A plug hole reaching the dielectric layer for capacitive element is formed in the interlayer insulating layer. Upper electrodes are formed to fill in the plug hole and positioned opposite to the lower electrode with the dielectric layer for capacitive element interposed. The dielectric layer for capacitive element is in contact with the upper surface of the lower electrode at a region directly below the plug hole and a region outside the sidewall of the plug hole. Thus, a semiconductor device having a capacitive element with a greater capacitance which prevents diffusion of metal atoms from the lower electrode as well as a manufacturing method thereof are provided.

Abstract: In a sampling inspection managing system, for each processing step, a setting is made on a processing flow table as to whether the processing step concerned is a step for determining the sampling inspection frequency of a specific inspection step. For a processing step which is set as “being a step for determining the sampling inspection frequency”, the inspection frequency of the specific inspection step is set on a sampling frequency setting table for every kind of product to be processed. Further, for the processing step, the processing number of lots is counted for every kind of product in a count table, and, on the basis of the processing number thus counted, a judgment is made as to whether each lot is a lot to be inspected in the specific inspection step. The judgment result is stored as information for the lot in a lot table. Accordingly, the inspection can be carried out at an inspection frequency suitable for every kind of product.

Abstract: There are described a semiconductor device having multilayer wiring and a method for manufacturing the semiconductor device, wherein an interconnection hole for interconnecting an upper wiring layer to a lower wiring layer is formed correctly, thereby improving the reliability of multilayer wiring. A lower silicon oxide film, an upper silicon oxide film, and a silicon nitride film to be interposed therebetween are formed on a spin-on-glass (SOG) film. Enlarged openings for interconnection holes are formed only within the upper silicon oxide film while the silicon nitride film is used as an etch stopper, thereby preventing extension of the enlarged openings to the SOG film.

Abstract: First, a hole pattern or a separation pattern of a first resist that is capable of supplying acid is formed on a semiconductor substrate. Then, a crosslinked film (organic frame) is formed on the side wall of the first resist pattern to obtain a resist pattern having a reduced hole diameter or separation width. Then, the hole diameter or the separation width is further reduced by causing thermal reflow of the crosslinked film. Finally, the semiconductor substrate is etched by using a resulting resist pattern as a mask.

Abstract: A semiconductor device of the present invention is provided with a first metal wire formed above a semiconductor substrate with an interlayer insulating film intervened, a fuse formed on interlayer insulating film so as to be spaced at a distance away from first metal wire, an insulating film which covers first metal wire and which has an opening above fuse, a second metal wire formed on insulating film, a first passivation film which covers second metal wire and fuse, and a second passivation film formed on first passivation film, made of a material different from that of first passivation film and having an opening above fuse.

Abstract: There is described a semiconductor manufacturing apparatus for coating the surface of a semiconductor wafer with an organic coating, such as anti-reflective coating, which shortens a down time required in association with removal of compounds that tend to sublime and enables simplification of removal of the compounds and an increase in safety of the removal operation. A top plate of a hot plate unit for heating a semiconductor wafer is formed from light-transmissive material such as quartz. A light source unit for illuminating UV-rays effective for decomposing organic compounds is disposed on the top plate. The hot plate unit bakes the semiconductor wafer coated with the organic material, and compounds that have a tendency to sublime including organic material adhere to the lower surface of the top plate in association with the baking operation.

Abstract: A method of manufacturing a semiconductor device is provided, which prevents a polyimide film from coming unstuck from a film to be subjected to isotropic etching, and further prevents deposits adhered to respective side faces of the films from coming off, during a heat treatment for imidizing the polyimide film. Isotropic etching is performed on a silicon nitride film 4 using, as a mask, a polyimide film 5 having a predetermined pattern formed therein. Next, a heat treatment is carried out to imidize the polyimide film 5 prior to performing anisotropic etching on a silicon oxide film 3. During the heat treatment for imidizing the polyimide film 5, since deposits, which are to be generated by anisotropic etching, are not yet adhered to the respective side faces of the films, the polyimide film 5 does not come unstuck from the silicon nitride film 4. Further, the deposits which are adhered to the respective side face of the films after the heat treatment will not come off.

Abstract: The substrate carrier management system includes a pre-diffusion processing apparatus, a carrier cleaner, and a carrier conveyer. The pre-diffusion processing apparatus unloads a substrate from a supplied carrier in which the substrate is stored, performs predetermined processing on the substrate, and transfers the processed substrate stored in a carrier to be used after processing. The carrier cleaner cleans a carrier emptied as a result of taking a substrate out of the carrier. The carrier conveyer conveys a carrier between the pre-diffusion processing apparatus and the carrier cleaner. The empty carrier unloaded from the pre-diffusion processing apparatus is cleaned by the carrier cleaner, and the processed substrate is stored in the empty carrier. With this arrangement, it is possible to automatically change carriers and thereby continuously use a cleaned carrier in the subsequent step without using a dedicated carrier.

Abstract: There are described a semiconductor inspection system for inspecting recessed defects formed in a semiconductor wafer and a semiconductor device manufacturing method including an inspection step of inspecting recessed defects formed in a semiconductor wafer. The semiconductor inspection system and the semiconductor device manufacturing method enable the following operations: an operation of radiating a laser beam onto a semiconductor wafer; an operation of detecting light scattered from foreign particles, as a result of a laser beam being radiated onto the semiconductor wafer; an operation of converting the detected scattered light into an electric signal; and an operation of outputting information about the recessed defects formed in the semiconductor wafer by means of subtracting the data pertaining to only the foreign particles located on the semiconductor wafer from the data pertaining to both the foreign particles and recessed defects formed in the semiconductor wafer.

Abstract: A process selection system and method enable the automatic control of the specification to equipment most suitable for each lot. Processing using this specific equipment can be performed by further selecting the most suitable equipment from equipment used for the product type. Since a plurality of equipment can be specified for each lot, the equipment can be specified from an equipment group having these plurality of equipment. The adequate number of products in process for each equipment-specific process equipment id can be calculated based on the distribution percentage ri. The equipment-specific process equipment having the maximum value of the differential Gi between the adequate number of products in process ni and the collected actual number of products in process can be determined as the equipment-specific process equipment for the lot.

Abstract: A power module includes a box-shaped smoothing capacitor (20) for smoothing a DC supply voltage to be externally applied to a power semiconductor device (5). The smoothing capacitor (20) is in contact with a side surface of a case frame (6) including a side (along which an N-terminal (8N) and a P-terminal (8P) are arranged) of a top surface of the case frame (6), and has a top surface level with the top surface of the case frame (6). An N-electrode (21N) and a P-electrode (21P) of the smoothing capacitor (20) are disposed on the top surface of the smoothing capacitor (20) and in proximity to the N-terminal (8N) and the P-terminal (8P) of a power module body portion (99), respectively. The power module can reduce a circuit inductance, is reduced in size and weight, and has good resistance to vibration.

Abstract: A dielectric layer for capacitive element is formed on a lower electrode. An interlayer insulating layer is formed on the lower electrode and the dielectric layer for capacitive element. A plug hole reaching the dielectric layer for capacitive element is formed in the interlayer insulating layer. Upper electrodes are formed to fill in the plug hole and positioned opposite to the lower electrode with the dielectric layer for capacitive element interposed. The dielectric layer for capacitive element is in contact with the upper surface of the lower electrode at a region directly below the plug hole and a region outside the sidewall of the plug hole. Thus, a semiconductor device having a capacitive element with a greater capacitance which prevents diffusion of metal atoms from the lower electrode as well as a manufacturing method thereof are provided.

Abstract: A substrate testing apparatus includes a first rail group made of a plurality of rails disposed in parallel with each other, a second rail group made of a plurality of rails disposed in parallel with each other in a direction that crosses the first rail group, a plurality of probe units disposed to cover respective intersections of the rails included in the first rail group and the rails included in the second rail group and being movable along the rails included in the first rail group and the second rail group, and corresponding interval maintaining means for keeping each rail included in the first rail group at an interval corresponding to an arrangement of locations to be measured on a substrate subjected to measurement, wherein the plurality of probe units each include a probing needle to be brought into contact with a surface of the substrate.

Abstract: An insulator film provided on a region for arranging a Zener diode has a plurality of groove portions successively arranged in a direction D1 of extension of each semiconductor region forming the diode. Each groove potion extends in a width direction D2 of each semiconductor region, and has a depth T3. Each semiconductor region is arranged on the upper surface of the insulator film. Therefore, it follows that each semiconductor region has a plurality of irregular shapes arranged in the direction D1 of extension and the Zener diode has a peripheral length not only in the transverse direction D1 but also in a vertical direction D3, so that a p-n junction area in the Zener diode is increased. Thus, parasitic resistance of an input protection Zener diode is reduced for improving a gate insulator film protective function of the diode.