Patents Assigned to Ryoden Semiconductor System Engineering Corporation
  • Patent number: 5996242
    Abstract: A nozzle and an exhaust member are provided opposite to each other with an upward opening of a processing vessel interposed therebetween. A side wall of the processing vessel is smoothly curved inward as the opening is approached upward. The nozzle spouts a nitrogen gas fed from a nitrogen gas feeder as a jet for covering the opening toward an exhaust port of the exhaust member. The jet can effectively function as a curtain because the side wall of the processing vessel is curved. Therefore, a cooling coil necessary for a conventional apparatus is not required. Consequently, instability of the state of the IPA vapor caused by the cooling coil can be eliminated so that defective dryness is relieved or eliminated.
    Type: Grant
    Filed: September 23, 1997
    Date of Patent: December 7, 1999
    Assignees: Ryoden Semiconductor System Engineering Corporation, Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akinori Matsumoto, Takeshi Kuroda, Cozy Ban, Toko Konishi, Naoki Yokoi
  • Patent number: 5994227
    Abstract: An improved etching method allowing the formation of a silicon nitride film with an adequate film thickness at the sidewall portion of a pattern is disclosed. A silicon nitride film formed to cover a stepped pattern is dry-etched, employing plasma of mixed gases containing CH.sub.2 F.sub.2 and O.sub.2. As a result, a sidewall spacer of the silicon nitride film is formed at the sidewall of the pattern in a self-aligned manner.
    Type: Grant
    Filed: July 20, 1998
    Date of Patent: November 30, 1999
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Hiroshi Matsuo, Takuji Oda, Yuichi Yokoyama, Kiyoshi Maeda, Shinya Inoue, Yuji Yamamoto
  • Patent number: 5963815
    Abstract: An amorphous silicon conductive film on a semiconductor wafer is treated with hydrofluoric acid to remove a natural oxide film therefrom, and then a very thin oxide film is formed on the semiconductor wafer. Thereafter, a silane gas is used to form a nucleating film, followed by annealing to cause the surface of the conductive film be roughened. The very thin oxide film is formed in a thickness of 0.5 angstroms to 20 angstroms. The very thin oxide film is alternatively formed either by treatment with an aqueous hydrofluoric acid solution or by flushing treatment. Thus, a roughened surface having a satisfactory roughness is uniformly formed on the surface of a conductive film on a semiconductor wafer.
    Type: Grant
    Filed: January 21, 1998
    Date of Patent: October 5, 1999
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Yoshihiko Okamoto, Tadashi Yoshida, Hiroshi Ohnishi, Kenichi Hanaoka, Shigeki Nakajima, Junichi Tsuchimoto
  • Patent number: 5934566
    Abstract: The present invention is directed to providing an apparatus which is improved so as to remove a contamination on a substrate efficiently. This apparatus includes a jet nozzle jetting out droplets toward a substrate. A liquid supply device and a gas supply device are connected to the jet nozzle. A mixing device mixing a liquid and a gas supplied to the jet nozzle and changing the liquid into the droplets is provided in the jet nozzle.
    Type: Grant
    Filed: August 11, 1997
    Date of Patent: August 10, 1999
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Itaru Kanno, Toshiaki Ohmori, Hiroshi Tanaka, Nobuaki Doi
  • Patent number: 5929482
    Abstract: An n.sup.+ semiconductor substrate (1) using a silicon wafer as a base material and including As includes oxygen of which the concentration is in the range of 12E17 atoms/cm.sup.3 to 20E17 atoms/cm.sup.3. The first epitaxial growth layer (2) of n type and a diffusion layer (3) of p type are formed in sequence on the second major surface (1S2) of the semiconductor substrate (1). The thickness of an epitaxial a growth layer (10) is set to be not more than 20 .mu.m. A trench (6) is formed so as to extend from a surface of the diffusion layer (3) to the inside of the first epitaxial growth layer (2). A gate oxide film (5) is formed on a bottom surface (6B) and a wall surface (6W) of the trench (6) and a conductive layer (11) fills the trench (6). An n-type source layer (4) is formed at a corner (6C) of the trench (6). After that, predetermined electrodes are formed and so on, to complete a device.
    Type: Grant
    Filed: April 16, 1998
    Date of Patent: July 27, 1999
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Minoru Kawakami, Mitsuhiro Yano, Yasunori Yamashita, Hidetoshi Souno
  • Patent number: 5905650
    Abstract: Failures detected by a tester are collated with defects detected by a defect checking device (Step S6). The collation is performed by retrieving defects coincident with each failure within a tolerance R0. Based on a mean value of displacements between the failures and the defects which are coincident with each other, coordinate values of the defects are corrected (Step S10). The coordinate values are corrected only when a collating ratio S that is a ratio of failures with which defects are coincident to whole failures exceeds a constant value S0 (Step S7). As a result, a coordinate value of a defect having high precision is obtained.
    Type: Grant
    Filed: September 16, 1997
    Date of Patent: May 18, 1999
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Toshikazu Tsutsui, Masaaki Furuta
  • Patent number: 5885858
    Abstract: A thin-film transistor (3, 5a, 5b and 5c) is covered with a first silicon nitride film (9) formed by an LPCVD method. A first silicon oxide film (6) is formed on the first silicon nitride film (9). A silicon nitride film (7), i.e., passivation film which is formed by a plasma CVD method is provided on the first silicon oxide film (6).
    Type: Grant
    Filed: January 2, 1998
    Date of Patent: March 23, 1999
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Hisayuki Nishimura, Shigeto Maegawa, Shigenobu Maeda
  • Patent number: 5844850
    Abstract: Data containing defect position coordinates obtained based on the result of physical inspection of a foreign material, a defect and the like at a surface of a semiconductor wafer by a defect inspecting apparatus is stored in storage means. Data of physical position coordinates obtained based on fail bit data from a tester is stored in storage means. Data indicating an additional failure region is produced by additional failure region estimating means based on the fail bit data, and is stored in storage means. Collating means produces data of corrected physical position coordinates by adding the data of limitation by failure mode stored in storage means to the data of physical position coordinates stored in storage means, and collates the data of corrected physical position coordinates with data of defect position coordinates stored in storage means.
    Type: Grant
    Filed: March 21, 1996
    Date of Patent: December 1, 1998
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Toshikazu Tsutsui, Tohru Koyama, Fumihito Ohta, Yasukazu Mukogawa, Masaaki Furuta, Yohji Mashiko
  • Patent number: 5803938
    Abstract: A liquid vaporizing apparatus includes a container for holding a liquid at a constant temperature with a temperature adjustment unit and a gas that does not react with the liquid is bubbled through the liquid in the container to vaporize the liquid. The container for holding the liquid has an internal space above the liquid and a second temperature adjustment unit for controlling the temperature of the internal space separately from the temperature of the liquid in the container. Since the internal space is maintained at a constant temperature, higher than the temperature of the liquid, the quantity of the vaporized liquid produced is stable.
    Type: Grant
    Filed: May 15, 1997
    Date of Patent: September 8, 1998
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Tooru Yamaguchi, Kouichirou Tsutahara, Takayuki Suenaga
  • Patent number: 5792314
    Abstract: A photosensitive resin removing method is capable of completely removing a photosensitive resin employed as a photoresist in an etching process for etching an aluminum film, and its derivatives and of improving the durability of a photosensitive resin removing apparatus for carrying out the method. A mixed gas is produced by mixing fluorine compound gas and steam, the mixed gas is excited with microwaves, and the photosensitive resin is exposed to the excited mixed gas to gasify the photosensitive resin.
    Type: Grant
    Filed: April 27, 1995
    Date of Patent: August 11, 1998
    Assignees: Ryoden Semiconductor System Engineering Corporation, Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroyuki Shima, Tadashi Nishioka
  • Patent number: 5785902
    Abstract: A liquid vaporizing apparatus includes a container for holding a liquid at a constant temperature with a temperature adjustment unit and a gas that does not react with the liquid is bubbled through the liquid in the container to vaporize the liquid. The container for holding the liquid has an internal space above the liquid and a second temperature adjustment unit for controlling the temperature of the internal space separately from the temperature of the liquid in the container. Since the internal space is maintained at a constant temperature, higher than the temperature of the liquid, the quantity of the vaporized liquid produced is stable.
    Type: Grant
    Filed: May 5, 1997
    Date of Patent: July 28, 1998
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Tooru Yamaguchi, Kouichirou Tsutahara, Takayuki Suenaga
  • Patent number: 5772842
    Abstract: A pellicle stripping apparatus includes a supporting section for supporting a photomask, the supporting section having gripping portions for gripping at least two edges of a pellicle frame of a pellicle adhered to the photomask; and a steam generating section for generating high temperature steam and contacting the pellicle adhered to the photomask with the steam, the steam generating section including a container having a steam vent directly opposite a portion of the pellicle adhered to the photomask and a heater for boiling water in the container.
    Type: Grant
    Filed: November 22, 1995
    Date of Patent: June 30, 1998
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Shinichiro Tanaka, Sigeru Wada, Haruhiko Kusunose
  • Patent number: 5767974
    Abstract: An apparatus and method for inspecting photomask pattern defects, discriminating true defects from false ones, efficiently detects only the true defects. The apparatus includes a light source; an irradiation section for transmitting light from the light source to a photomask; a light detecting section for detecting the light passing through transparent parts of the photomask; an image processing section for acquiring image data of the pattern according to signals from the light detecting section; a first condition setting section for setting a coordinate threshold that defines a misregistration defect in the pattern; a second condition setting section for setting an area threshold that defines an area defect of the pattern; a testing section that determines whether the coordinates of a pattern feature and the area of the pattern satisfy the thresholds upon comparison to a second pattern; and an output section for outputting a signal indicating a defect only when at least one of the thresholds is exceeded.
    Type: Grant
    Filed: January 17, 1996
    Date of Patent: June 16, 1998
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Hisayoshi Higashiguchi, Kunihiro Hosono
  • Patent number: 5746233
    Abstract: Obtained are a washing apparatus inhibiting a washing liquid from losing its washability and a method therefor. A circulating pump (5) circulates a washing liquid (3) successively through a heater (6), a filter (7), and an overflow washing tank (2). The washing liquid (3) is gradually evaporated. On the other hand, a water supplier (10) supplies the overflow washing tank (2) with water through a tube (8). An amine supplier (11) supplies the overflow washing tank (2) with amines through a tube (9). A control unit (12) controls the quantities of the water and amines as supplied. In a washing part (50), therefore, the quantities of the water and amines are inhibited from being reduced upon a lapse of time from operation starting, whereby the washing liquid (3) is inhibited from losing its washability.
    Type: Grant
    Filed: July 11, 1996
    Date of Patent: May 5, 1998
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Takeshi Kuroda, Itaru Kanno
  • Patent number: 5747843
    Abstract: An improved semiconductor memory device in which an electric circuit operates normally is provided. A block of memory cells of a dynamic random access memory is provided on a semiconductor substrate. A dummy storage node is provided near a corner portion of the memory cell block. A dummy cell plate is provided such that it covers the dummy storage node and is electrically insulated from a main cell plate of the DRAM.
    Type: Grant
    Filed: June 21, 1996
    Date of Patent: May 5, 1998
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Hiroshi Matsuo, Shinya Watanabe, Yuichi Yokoyama, Shinya Inoue
  • Patent number: 5736745
    Abstract: A sample placement portion is fixed to a frame. A stage and a cylindrical piezoelectric element are attached to the sample placement portion, and on this piezoelectric element, a sample (i.e., a semiconductor wafer) is positioned. A light collecting portion and a light receiving portion integrated together are attached slidably to frame for detecting the number and locations of contaminants. In addition, an analyzing portion for analyzing the types of the contaminants is slidably attached to the frame. Accordingly, it is made possible to reduce the size of the apparatus and to perform a highly reliable evaluation of the contamination.
    Type: Grant
    Filed: April 4, 1996
    Date of Patent: April 7, 1998
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Makiko Nagashima, Tadashi Nishioka
  • Patent number: 5736438
    Abstract: In a miniaturized complete CMOS SRAM of a TFT load type, a field effect thin-film transistor (TFT) can achieve stable reading and writing operation of a memory cell and can reduce power consumption thereof. The field effect thin-film transistor formed on an insulator includes an active layer and a gate electrode. The gate electrode is formed on a channel region of the active layer with a gate insulating film therebetween. The active layer is formed of a channel region and source/drain regions. The channel region is formed of a monocrystal silicon layer and does not includes a grain boundary. The source/drain regions is formed of a polysilicon layer. The channel region has a density of crystal defects of less than 10.sup.9 pieces/cm.sup.2. The thin film transistor shows an ON current of 0.25 .mu.A/.mu.m per channel width of 1 .mu.m and an OFF current of 15 fA/.mu.m. The thin-film transistor can be applied to a p-channel MOS transistor serving as a load transistor in a memory cell of a CMOS type SRAM.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: April 7, 1998
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Hisayuki Nishimura, Kazuyuki Sugahara, Shigenobu Maeda, Takashi Ipposhi, Yasuo Inoue, Toshiaki Iwamatsu, Mikio Ikeda, Tatsuya Kunikiyo, Junji Tateishi, Tadaharu Minato
  • Patent number: 5723982
    Abstract: A method and apparatus for measuring electrical characteristics of a thin surface layer of a sample such as a semiconductor element. A triangular pulse wave of is applied between the sample and a probe needle on a cantilever. By measuring current that flows through the thin surface layer of the sample using the probe needle, I/V characteristics are obtained. A control circuit keep constant the clearance between the probe needle and the thin surface layer of the sample by applying a voltage to a piezoelectric element that supports the sample. I/V characteristics are then measured at a plurality of test points on the thin surface layer of the sample.
    Type: Grant
    Filed: July 25, 1995
    Date of Patent: March 3, 1998
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Takao Yasue, Tadashi Nishioka
  • Patent number: 5720814
    Abstract: A supporting plate is disposed above a rotating stage to drive rotatively a semiconductor wafer mounted thereon, and a nozzle fitting rotating disk is secured to the supporting plate rotatively. The rotating center of the nozzle fitting rotating disk is disposed at a position eccentric from a central axis line of the rotating stage. At least one nozzle group in rows composed of a plurality of nozzles for ejecting a photoresist on the semiconductor wafer is fitted to the nozzle fitting rotating disk at intervals in a radial direction of the disk. At least one fitting position of the plurality of nozzles composing nozzle groups is adjustable.
    Type: Grant
    Filed: February 21, 1996
    Date of Patent: February 24, 1998
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Motoshi Takagi, Tadashi Nishioka
  • Patent number: 5709037
    Abstract: A material to be dried, such as a semiconductor substrate during manufacturing a semiconductor device, is loaded into a process chamber fitted at a loading opening with a lid which is closed from above. The inner side wall surface of the process chamber has a first surface formed in the lower part thereof and is substantially in parallel with the inner wall surface of the lid, and a second surface extending from the upper end part of the first surface and bent outwards to face the inner wall surface of the lid. A processing solution vapor is fed through a steam supply port in the second surface into the process chamber and flowed downwardly over the material to be dried. The processing solution vapor is condensed and recovered below the material to be dried.
    Type: Grant
    Filed: October 7, 1996
    Date of Patent: January 20, 1998
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Hiroshi Tanaka, Nobuaki Doi, Masashi Omori, Hiroaki Ishikawa