Abstract: A memory device includes control circuitry configured to perform an erase operation to erase memory cells of a memory block and perform an erase verify operation to verify whether the memory cells were sufficiently erased. To perform the erase operation, the control circuitry is configured to supply a first erase voltage pulse, perform the erase verify operation subsequent to supplying the first erase voltage pulse, subsequent to the erase verify operation, supply a first bias voltage to a first one of a plurality of memory strings and a second bias voltage different than the first bias voltage to a second one of a plurality of memory strings, and, while supplying the first and second bias voltages, supply a second erase voltage pulse. The second bias voltage is configured to inhibit the second erase voltage pulse supplied to the memory cells of the second one of the plurality of memory strings.

Abstract: A method includes performing a chemical mechanical polishing (CMP) process on a wafer in a CMP apparatus, loading the wafer into a roll cleaning apparatus after performing the CMP process on the wafer, applying a fluid on a surface of the wafer; brushing the surface of the wafer with a rotating roll brush, and measuring a distribution of the fluid on the surface of the wafer while brushing the surface of the wafer.

Abstract: To reduce data disturbs and lower current requirements of a 3D NAND memory die, a multi-block plane of non-volatile memory cells has its source line separated into multiple source line regions by introduction of isolation trenches. The plane structure for the NAND memory is maintained, but is broken into multi-block sub-planes, each with an independently biasable source line.

Abstract: A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using this machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service.

Abstract: Post-write data management operations, such as refresh read, data scrub, and data relocation, are typically performed after a certain period of time has elapsed. However, performing such operations based on probability of access can provide advantages. So, in one example, a post-write data management operation is performed more frequently on relatively-warmer data than on relatively-colder data.

Abstract: A data storage device includes a controller. The controller includes a controller memory buffer (CMB). The controller is configured to associate both the CMB and a host memory buffer (HMB) of a host device as a single buffer pool with a plurality of CMB buffers and a plurality of HMB buffers. The controller is further configured to allocate either a CMB buffer or a HMB buffer based on a tradeoff between latency and performance between using the CMB or using the HMB to store data. By leveraging the benefits of both the CMB and the HMB to store data, the overall performance of the data storage device may be improved.

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.

Abstract: The memory device that includes a die with a CMOS wafer with programming and erasing circuitry. The die also includes a plurality of array wafers coupled with and in electrical communication with the CMOS wafer and having different programming and erasing efficiencies. Each of the array wafers includes memory blocks with memory cells. The control circuitry of the CMOS wafer is configured to output at least one of different initial programming voltages and unique erase voltages to the plurality of array wafers.

Abstract: Some data storage devices select blocks of memory from a free block pool and randomly allocate the blocks as primary and secondary blocks to redundantly store data in a write operation. However, some blocks, such as blocks on the edge of a plane, may not serve well as primary blocks. One example data storage device presented herein addresses this problem by allocating such blocks as secondary blocks instead of primary blocks.

Abstract: A spin-transfer torque (STT) magnetoresistive memory device includes a first electrode, a second electrode, and a magnetic tunnel junction located between the first electrode and the second electrode. The magnetic tunnel junction includes a reference layer having a fixed magnetization direction, a free layer stack, and a nonmagnetic tunnel barrier layer located between the reference layer and the free layer stack. The free layer stack has a total thickness of less than 2 nm, and contains in order, a proximal ferromagnetic layer located proximal to the nonmagnetic tunnel barrier layer, a first non-magnetic metal sub-monolayer, an intermediate ferromagnetic layer, a second non-magnetic metal sub-monolayer, and a distal ferromagnetic layer.

Abstract: A vehicle battery includes at least one battery cell and a battery controller for charging the at least one battery cell via a power interface of the vehicle battery. The vehicle battery further includes a battery memory and a data interface to transfer data between the battery memory and a data device external to the vehicle. A data storage controller of the vehicle battery transfers, via the data interface, data between the battery memory and the data device while the vehicle battery is removed from the vehicle. In one aspect, the data device performs at least one of transferring data from a battery memory to a memory of the data device and transferring data from the memory of the data device to the battery memory while the data device is physically connected to the vehicle battery.

Abstract: The present disclosure generally relates to improved address translation. Rather than fetching translated addresses using ATS/ATC, a HIM address translation search engine (HATS) is used through implementing the ATC in a layer above per an NVMe command. The HATS is an engine that will monitor pointers with untranslated addresses and will fetch the translated addresses for the pointers. Once the translated addresses are fetched for the pointer, the HATS will overwrite the untranslated address with the translated address. The HATS will then update the status of the pointers. When a translation request fails, the device will use PRI to request the translated address. During a translation request fail the device will drain any incoming requests while skipping the data transfer phase. The device will not block any other requests in a queue. Once that translated address is received through the PRI flow, the status of the pointer will be updated.

Abstract: There is a large latency and controller bandwidth associated with moving data between dies or between memory devices. The controller includes one or more flash interface modules (FIMs) that are utilized to write data to the memory device and read data from the memory device. Each of the one or more FIMs includes one or more switches. Each switch is utilized to transfer data from a source block to a destination block. Likewise, rather than using a memory external to the FIM to cache the data, the data is stored in a FIM cache and moved from the FIM cache to the relevant physical layer to be programmed to the destination block. Because data is not being transferred to the system memory, the latency and bandwidth associated with relocating data may be decreased.

Abstract: The present disclosure generally relates to memory management during SGL fetching. When a data storage device is required to fetch an SGL from a host device, the data storage device cannot determine how much memory will be required to be allocated. The disclosure herein reduces the impact of the problem of under or over allocating memory and over-fetching, thereby reducing performance of the device during transfers. The disclosure provides guidance on how to implement an adaptive learning process based upon statistic collection of SGL fetches. By maintaining a table of statistics, the data storage device controller may learn and more closely predict an amount of memory to allocate for SGL fetching.

Abstract: The disclosure relates in some aspects to an apparatus that includes stages of a failure event counting circuit including an Nth stage where N refers to an arbitrary stage of the stages of the failure event counting circuit. The Nth stage may include an Nth fuse trigger circuit configured to receive an event detector signal indicative of a failure event, an Nth electronic fuse configured to disconnect a circuit path between a voltage source and a ground in response to the event detector signal, and an Nth delay circuit coupled to the Nth e-fuse and configured to cause a time delay for activating a subsequent stage of the failure event counting circuit in response to the Nth e-fuse disconnecting. In this aspect, each of the stages of the failure event counting circuit may be configured to use the respective e-fuse to record a discrete failure event.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and memory opening fill structures vertically extending through the alternating stack. An insulating liner overlies stepped surfaces of the alternating stack in a staircase region. A plurality of discrete dielectric plates can be formed over the insulating liner. In one embodiment, the plurality of discrete dielectric plates can function as etch stop structures for formation of contact via structures that contact underlying portions of the electrically conductive layers. In another embodiment, the plurality of discrete dielectric plates may be replaced with a metallic material that forms extensions of the electrically conductive layers, and can be employed as etch stop structures during formation of contact via structures.

Abstract: An apparatus is provided that includes a memory structure including non-volatile memory cells, a first processor and a second processor. The first processor is configured to provide a plurality of sets of commands to a second processor to perform memory operations on the non-volatile memory cells. The second processor is configured to execute the sets of commands and provide a control signal to the first processor. The first processor is further configured to provide the sets of commands to the second processor based on a status of the control signal. The second processor is further configured to control the status of the control signal so that the second processor executes sets of commands with no idle time between consecutive sets of commands.

Abstract: A semiconductor structure includes a semiconductor substrate containing a shallow trench isolation structure that laterally surrounds a transistor active region, at least one line trench vertically extending into the semiconductor substrate, and a source region and a drain region located in the transistor active region. A contoured channel region continuously extends from the source region to the drain region underneath the at least one line trench. A gate dielectric contacts all surfaces of the at least one line trench and extends over an entirety of the contoured channel region. A gate electrode containing at least one fin portion overlies the gate dielectric.

Abstract: A data storage device includes storage media and control circuitry and is configured to enable the creation of partitions with different performance levels. The storage media includes a first set and a second set of memory blocks having different performance levels. The control circuitry is configured to: in response to a request from a host system, provide performance data from the first set of memory blocks and the second set of memory blocks to the host system. The control circuitry is further configured to: receive partition settings from the host system, the partition settings creating a first partition including at least part of the first set of memory blocks and a second partition including at least part of the second set of memory blocks, wherein the first partition has a better performance level than the second partition; and save the partition settings to the storage media.

Abstract: A stack of alternating layers of dielectric and conductive materials are formed on a substrate. A first portion of the stack of alternating layers forms a plurality of blocks of NAND memory. A second portion of the stack of alternating layers forms a configurable capacitor structure. The configurable capacitor structure is configurable to form one or more capacitors of configurable capacitance.