Abstract: A plurality of memory programming the memory cells to at least one programmed data state in a plurality of program-verify iterations. In each iteration, after a programming pulse, a sensing operation is conducted to compare the threshold voltages of the memory cells to a low verify voltage associated with a first programmed data state and to a high very voltage associated with the first programmed data state. The sensing operation includes discharging a sense node through a bit line coupled to one of the memory cells and monitoring a discharge time of the sense node. At least one aspect of the sensing operation is temperature dependent so that a voltage gap between the high and low verify voltages is generally constant across a range of temperatures.

Abstract: Technology is disclosed herein for a memory system that balances peak Icc with programming speed. A memory system applies voltages to respective word lines during a verify operation that balances peak Icc with programming speed. The voltages for which the ramp rate is controlled include a read pass voltage applied to unselected word lines and a spike voltage applied to the selected word line at the beginning of the verify. The ramp rate of the voltages is slow enough to keep the peak Icc during verify to a target peak Icc regardless of which word line is selected for verify. However, the ramp rate of the voltages to the word lines during verify is fast enough to make use of the target peak Icc in order achieve faster programming. Therefore, the impact on programming time is minimized while staying within the allowed peak Icc.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines including at least one edge word line and other data word lines. The memory cells are arranged in strings and are configured to retain a threshold voltage corresponding to data states. The strings are organized in rows and a control means is coupled to the word lines and the strings and identifies the at least one edge word line. The control means programs the memory cells of the strings in particular ones of the rows and associated with the at least one edge word line to have an altered distribution of the threshold voltage for one or more of the data states compared to the memory cells of the strings not in particular ones of the rows and not associated with the at least one edge word line during a program operation.

Abstract: Technology is disclosed herein for a memory system that compensates for different programming speeds in two sets of memory cells when reading those two sets of memory cells. The memory system programs a group of the memory cells to one or more data states. In one aspect, the memory cells are not verified during programming. The group has a first set of memory cells that program at a first speed and a second set of memory cells that program at a second speed. The memory system reads the first set of the memory cells with a first set of read parameters and reads the second set of the memory cells with a second set of read parameters. The first set of read parameters are different from the second set of read parameters to compensate for the different programming speeds.

Abstract: The memory device includes at least one memory block with a plurality of memory cells arranged in a plurality of word lines. The memory device includes control circuitry that is configured to program the memory cells of the at least one memory block in a plurality of program loops. The control circuitry is further configured to receive a command to write user data to the memory device. On at least a portion of a selected word line of the plurality of word lines, the control circuitry is configured to perform a smart verify operation to acquire a smart verify programming voltage. After the smart verify programming voltage is acquired, in a plurality of program loops, the control circuitry is configured to program the memory cells of the selected word line to include the user data and data that corresponds to the smart verify programming voltage.

Abstract: An apparatus includes memory cells connected to word lines and disposed in strings each defining a channel and coupled to bit lines and a source line. The memory cells are configured to retain a threshold voltage corresponding to data states. A control means is configured to apply programming pulses followed by verification pulses of program verify voltages associated with the data states to the word lines during a program operation. The control means ramps a selected word line voltage applied to the word lines from one of the program verify voltages to approximately zero while ramping voltages applied to the bit lines and the source line to a high supply voltage during a pre-charge operation. The control means ramps an assist voltage applied to a pre-charge assist portion of the memory apparatus to generate gate-induced drain leakage current in the strings and pre-charge the channel during the pre-charge operation.

Abstract: A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The word line switches are arranged in groups of X word line switches such that each group of X word line switches is positioned in a line under Y blocks of non-volatile memory cells and has a length that is equal to the width of the Y blocks of non-volatile memory cells. To allow closer placement of word line switches that supply different blocks and support the possible large voltage differences between their transistors, word line switches supplying different blocks are formed over a single active region and separated by an intermediate control gate set to be off.

Abstract: In a multi-tiered non-volatile memory structure that can perform operations on sub-blocks, performance of the different tiers/sub-blocks is made consistent by using different word line to word line pitches in the different tiers/sub-blocks.

Abstract: Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural network when the available training data set is sparse through use of a generative adversary network (GAN).

Abstract: Systems and methods for bit line modulation to compensate for cell source variation are disclosed. For example, a method for reading data from non-volatile storage comprising determining a first bit line level based on a first programmed data state that is being sensed and determining a second bit line level based on a second programmed data state that is being sensed. As another example, a storage device comprising a first bit line driver configured to generate a first bit line level for a first set of bit lines corresponding to a first set of memory strings based on a first cell source level associated with the first set of memory strings a second bit line driver configured to generate a second bit line level for a second set of bit lines corresponding to a second set of memory strings based on a second cell source level associated with the second set of memory strings.

Abstract: Technology is disclosed herein for preventing erase disturb in NAND. Erase voltages are applied to a source line and bit lines associated with selected memory cells, while applying an erase enable voltage to word lines connected to the selected cells. Preventing erase disturb may include raising the channel potential of unselected memory cells to a source line voltage that has a sufficiently low magnitude to not erase the unselected cells given a voltage on word lines connected to the unselected cells. The unselected cells share bit lines with the selected cells and may also share word lines. Preventing erase disturb may also include applying voltages to the select transistors that prevent the erase voltage from passing from the shared bit lines to the channels of the unselected cells. The voltages decrease from the bit lines to the unselected memory cells and may prevent GIDL generation. Current consumption is kept low.

Abstract: In order to lower the peak and average current through the channel (thereby lowering peak and average power consumption) during program-verify, which exhibits a word line dependency, the inventors propose to program dummy memory cells connected to a dummy word line before programming data memory cells connected to a data word line. The additional resistance in the NAND string introduced by the preprogrammed dummy memory cells will cause the peak current, and power consumption, to be lower. To address the word line dependency, the dummy memory cells connected to the dummy word line can be programmed to different threshold voltages based on which data word line is to be programmed. Thus, prior to programming data non-volatile memory cells connected to a particular data word line, the dummy memory cells are programmed to a threshold voltage that is chosen based on the position of the particular data word line.

Abstract: To reduce data disturbs and lower current requirements of a 3D NAND memory die, a multi-block plane of non-volatile memory cells has its source line separated into multiple source line regions by introduction of isolation trenches. The plane structure for the NAND memory is maintained, but is broken into multi-block sub-planes, each with an independently biasable source line.

Abstract: A non-volatile memory system comprises a plurality of non-volatile memory cells divided into three or more tiers. The memory cells can be programmed, erased and read. In order to achieve uniform erase speed for the three or more tiers, the erase process comprises applying a larger voltage bias to control gates of non-volatile memory cells in the outer tiers than the voltage bias applied to control gates of non-volatile memory cells in one or more inner tiers.

Abstract: An apparatus is provided that includes a word line coupled to a word line driver circuit, bit lines, a plurality of non-volatile memory cells each coupled to the word line and a corresponding one of the bit lines, and a control circuit coupled to the word line and the bit lines. The control circuit is configured to program the memory cells by causing the word line driver to apply a program pulse to the word line, and biasing each bit line to a corresponding bit line voltage that has a value that varies based on a distance between the word line driver and the corresponding bit line.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for persistent memory management. Persistent memory management may include replicating a persistent data structure in volatile memory buffers of at least two non-volatile storage devices. Persistent memory management may include preserving a snapshot copy of data in association with completion of a barrier operation for the data. Persistent memory management may include determining which interface of a plurality of supported interfaces is to be used to flush data from a processor complex.

Abstract: An apparatus is provided that includes an integrated circuit die that includes an uppermost metal layer of an integrated circuit fabrication process, a plurality of first bonding pads disposed on the uppermost metal layer at a first bonding pad pitch, a first additional metal layer disposed above the uppermost metal layer, and a plurality of second bonding pads disposed on the first additional metal layer at a second bonding pad pitch greater than the first bonding pad pitch. The apparatus further includes a plurality of conductors each electrically coupling a unique one of the first bonding pads to a corresponding one of the second bonding pads.

Abstract: An integrated controller, logic circuit and memory array (“CLM”) semiconductor device includes stacked controller, memory array logic circuit and memory array wafers, or individual dies diced therefrom, which together operate as a single, integrated semiconductor flash memory device. The memory array logic circuit dies and/or the memory array dies may be formed with full-thickness plated or filled vias connecting to bond pads on opposed surfaces of the dies. The bond pads of the respective stacked semiconductor dies may be aligned and affixed to each other to electrically and mechanically couple each of the semiconductor dies in the respective wafers together.

Abstract: An apparatus includes a control circuit and a plurality of non-volatile memory cells arranged in a plane of a memory die. The plane includes a first word line including a first word line portion coupled to a corresponding first group of the non-volatile memory cells, and a second word line including a second word line portion coupled to a corresponding second group of the non-volatile memory cells, the second word line different from the first word line. The control circuit is configured to apply a first voltage to the first word line portion and apply a second voltage to the second word line portion to concurrently read the first group of the non-volatile memory cells and the second group of the non-volatile memory cells. The first group of the non-volatile memory cells and the second group of the non-volatile memory cells each store less than a page of data.

Abstract: An apparatus includes a control circuit configured to connect to memory cells connected in series in NAND strings. Each NAND string includes a plurality of data memory cells coupled to a plurality of data word lines in series with a plurality of dummy memory cells connected to a plurality of dummy word lines. The control circuit configured to apply a first dummy word line voltage to one or more dummy word lines of the plurality of dummy word lines in a verify step of a program operation to program data memory cells. The control circuit is configured to apply a second dummy word line voltage to the one or more dummy word lines in a read operation to read the data memory cells.