Abstract: A storage device is disclosed herein. The storage device comprises: a non-volatile memory, where the non-volatile memory includes a block of N wordlines partitioned into a plurality of sub-blocks; and control circuitry coupled to the N wordlines. The control circuitry is configured to: determine a program status of an unselected sub-block of the plurality of sub-blocks before performing an operation on a selected sub-block of the plurality of sub-blocks; based on determining that the program status of the unselected sub-block is programmed, perform a precharge operation including applying a first precharge time; and based on determining that the program status of the unselected sub-block is not programmed, perform a precharge operation including applying a second precharge time, wherein the first precharge time is for a longer period than the second precharge time.

Abstract: An apparatus includes a control circuit configured to connect to NAND strings that are connected to bit lines, where each bit line is connected to a plurality of NAND strings in a corresponding plurality of regions of a block. The control circuit is configured to apply a read voltage in read operations directed to NAND strings of the plurality of regions of the block and subsequently adjust the read voltage by a first predetermined amount for read operations directed to NAND strings of a first region of the block. The control circuit is further configured to adjust the read voltage by a second predetermined amount for read operations directed to NAND strings of a second region of the block. The first and second predetermined amounts are based on respective locations of the first and second regions in the block.

Abstract: Apparatuses and techniques are described for reducing the number of latches used in sense circuits for a memory device. The number of internal user data latches in a sense circuit is reduced by using an external data transfer latch to store a bit of user data, in place of an internal user data latch. The user data in the data transfer latches identifies a subset of the data states which are not prohibited from having a verify test. The subset is shifted as the program operation proceeds, at specified program loops, to encompass higher data states. The completion of programming by a memory cell is indicated by the user data latches and another internal latch of the sense circuit in place of the external data transfer latch.

Abstract: A storage device is disclosed herein. The storage device comprises: a non-volatile memory, where the non-volatile memory includes a block of N wordlines partitioned into a plurality of sub-blocks and the plurality of sub-blocks includes a first sub-block of a first subset of the block of N wordlines and a second sub-block of a second subset of the block of N wordlines; and control circuitry coupled to the block of N wordlines. The control circuitry is configured to: perform a program operation in a normal order programming sequence on the first sub-block; perform a sensing operation on the first sub-block using a reverse sensing scheme; perform a program operation in a reverse order programming sequence on the second sub-block; and perform a sensing operation on the second sub-block using a regular sensing scheme.

Abstract: The memory device includes at least one memory block with source and drain sides and a plurality of memory cells arranged in a plurality of word lines. The word lines are arranged in a plurality of independently programmable and erasable sub-blocks. Control circuitry is configured to program the memory cells of a selected sub-block and determine a location of the within the at least one memory block and determine a programming condition of at least one unselected sub-block. The control circuitry is also configured to program at least one word line in the selected sub-block in a plurality of program loops that include pre-charging processes. The control circuitry pre-charges a plurality of channels from either the source or drain side based on at least one of the location of the selected sub-block within the memory block and the programming condition of the at least one unselected sub-block.

Abstract: The memory device includes a memory block, which includes a plurality of memory cells arranged in a plurality of word lines. The memory device also includes control circuitry in communication with the memory block. The control circuitry is configured to perform a programming operation to program the memory cells of a selected word line of the plurality of word lines. During the programming operation, the control circuitry is configured to apply a programming pulse VPGM to a selected word line to the selected word line, apply a first pass voltage to a first set of word lines of the plurality of word lines, the first set of word lines being adjacent the selected word line, and apply a second pass voltage to a second set of word lines of the plurality of word. The first pass voltage is greater than the second pass voltage.

Abstract: Technology is disclosed herein for managing timing parameters when programming memory cells. Timing parameters used sub-clocks in an MLC program mode may also be used for those same sub-clocks in a first SLC program mode. However, in a second SLC program mode a different set of timing parameters may be used for that set of sub-clocks. Using the same set of timing parameters for the MLC program mode and the first SLC program mode saves storage space. However, the timing parameters for the MLC program mode may be slower than desired for SLC programming. A different set of timing parameters may be used for the second SLC program mode to provide for faster program operation. Moreover, the different set of timing parameters used for the faster SLC program mode do not require storage of a separate set of timing parameters.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes drain-side select gate transistors for coupling to a drain-side of memory holes of memory cells and configured to retain a transistor threshold voltage. The memory holes are arranged in rows comprising strings. A control means is configured to program drain-side select gate transistors of the memory holes to an initial transistor threshold voltage using pulses increasing in magnitude by a first transistor step amount during each of a plurality of foggy loops of a foggy program operation. The control means is also configured to program the drain-side select gate transistors of the memory holes to a target transistor threshold voltage using pulses increasing in magnitude by a second transistor step amount during each of a plurality of fine loops of a fine program operation. The first transistor step amount is greater than the second transistor step amount.

Abstract: The memory device includes a plurality of memory blocks, each including a plurality of memory cells arranged in a plurality of word lines. Control circuitry is in communication with the plurality of memory blocks. In operation, the control circuitry receives a data write instruction and programs the memory cells of the memory blocks to a one bit per memory cell (SLC) format. In response to the data programmed to the memory cells of the memory blocks in the SLC format reaching an SLC limit prior to completion of the data write instruction, without erasing the memory cells programmed to the SLC format, the control circuitry programs the memory cells of at least some of the plurality of memory blocks from the SLC format to a two bits per memory cell (MLC) format.

Abstract: The techniques include a memory device receiving a data write instruction. The memory device programs the memory cells of the memory blocks to a one bit per memory cell (SLC) format with a first and second SLC data states. In response to the data programmed to the memory cells of the memory blocks reaching an SLC limit prior to completion of the data write instruction, without erasing the memory cells, the memory device programs at least some of the memory cells from the SLC format to a two bits per memory cell (MLC) format. When programming from the SLC format to the MLC format, the memory device inhibits programming of some of the memory cells in the first and second SLC data states to form a first MLC data state and programs other memory cells of the SLC data states to form second, third, and fourth MLC data states.

Abstract: Technology is disclosed herein for smart verify in a memory system that has a four bit per cell program mode (or X4 mode) and also a three bit per cell program mode (or X3 mode). The X3 mode uses a three-bit gray code that is based on a four-bit gray code of the X4 mode. The memory system skips verify of states in the X3 mode, while using a considerable portion of the programming logic from the X4 mode. In one X3 mode the memory system skips B-state verify while the number of memory cells having a Vt above an A-state verify voltage is below a threshold. In one X3 mode the memory system determines whether to skip verify for a first set of data states based on a first test and determines whether to skip verify for a second set of data states based on a second test.

Abstract: Technology is disclosed herein for mixed lockout verify. In a first programming phase, prior to a pre-determined data state completing verification, a no-lockout program verify is performed. After the pre-determined data state has completed verification, a lockout program verify is performed. The no-lockout verify may include charging all bit lines associated with the group to a sensing voltage to perform. The lockout verify may include selectively charging to the sensing voltage only bit lines associated with memory cells in the group to be verified. Bit lines associated with memory cells in the group that are not to be verified may be grounded to perform the lockout verify. The lockout verify saves considerable current and/or power. However, performing the lockout verify during the first programming phase may slow performance due to a need to scan the content in a remote set of data latches.

Abstract: A memory apparatus and operating method are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes and configured to retain a threshold voltage. The memory holes are organized in rows grouped in strings and the strings comprise a plurality of blocks which comprise planes. A control means is configured to program the memory cells connected to one of the word lines and associated with one of the strings in each of the plurality of planes and acquire a smart verify programming voltage individually for each of the planes in a smart verify operation. The control means concurrently programs at least some of the memory cells connected to each of the word lines in each of the planes in a program operation using the smart verify programming voltage individually acquired for each of the planes in the smart verify operation.

Abstract: An apparatus is provided that includes a block of memory cells having a NAND string that includes a first select transistor, and a control circuit coupled to the block of memory cells. The control circuit is configured to perform an erase operation on the block of memory cells by determining a first count of a number of times that the block of memory cells previously has been programmed and erased, determining based on the first count a first drain-to-gate voltage of the first select transistor, wherein the first drain-to-gate voltage is configured to cause the first select transistor to generate a first gate-induced drain leakage current, and applying a first erase pulse to the first select transistor based on the determined first drain-to-gate voltage.

Abstract: To reduce spikes in the current used by a NAND memory die, different ramp rates are used for the pass voltage applied to unselected word lines during a program operation depending on whether data is stored in a multi-level cell (MLC) format or in a single level cell (SLC) format. These ramp rates can be determined through device characterization and stored as parameter values on the memory die. Different ramp rate interval values can also be used for the pass voltage applied to unselected word lines during a program operation depending on whether data is stored in an MLC format or in an SLC format.

Abstract: A storage device comprises: a non-volatile memory including control circuitry and an array of memory cells formed using a set of word lines and a set of bit lines. A controller, coupled to the non-volatile memory, configured to: determine, based on a stage of a product lifetime of the non-volatile memory, a negative word line setting for implementing during performance of a first operation; perform the first operation, the first operation including adjusting, based on the negative word line setting, a negative word line relative parameter; determine, based on another stage of the product lifetime of the non-volatile memory, another negative word line setting for implementing during performance of a second operation; and perform the second operation, the second operation including adjusting, based on the other negative word line setting, another negative word line relative parameter.

Abstract: A memory apparatus and operating method are provided. The apparatus includes memory cells connected to word lines and disposed in strings and configured to retain a threshold voltage corresponding to data states. A control means is configured to program and verify the memory cells during a program operation. The memory cells associated with predetermined ones of the data states are not verified until the memory cells associated with specific prior ones of the data states finish programming to define verify windows ranging between each one of the specific prior ones of the data states and each one of the predetermined ones. The control means adjusts the verify windows in response to the memory cells associated with one of the specific prior ones of the data states not finishing programming before the one of the predetermined ones of the at least one of the verify windows is verified.

Abstract: To reduce spikes in the current used by a NAND memory die, different ramp rates for different regions, or zones, of word lines are used for the pass voltage applied to unselected word lines during a program operation. The properties of the word lines, such as their resistance and capacitance (RC) values, vary across the NAND memory array. By determining the RC values of the word lines across the array, the word lines can be broken into multiple zones based on these properties. The zones can then be individually assigned different ramp rates for applying a pass voltage to the unselected word lines, where a parameter for the ramp rates can be stored as a register value on the memory die.

Abstract: An apparatus includes a control circuit that is configured to connect to an array of non-volatile memory cells. The control circuit includes a first plurality of data latches configured to connect to non-volatile memory cells of a first plane and a second plurality of data latches configured to connect to non-volatile memory cells of a second plane. The control circuit also includes a shared data transfer data latch configured for transfer of data with the first plurality of data latches and the second plurality of data latches.

Abstract: The memory device has a plurality of memory blocks including a plurality of memory cells arranged in a plurality of word lines. The memory device also includes control circuitry that is in communication with the plurality of memory blocks. The control circuitry is configured to receive a data write instruction. The control circuitry is further configured to program the memory cells of the memory blocks to an SLC format. In response to the data programmed to the memory cells of the memory blocks in the SLC format reaching an SLC limit prior to completion of the data write instruction, without erasing the memory cells programmed to the SLC format, the control circuitry is configured to program the memory cells of at least some of the plurality of memory blocks from the SLC format to a TLC format.