Patents Assigned to SanDisk Technologies LLC
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Patent number: 10734408Abstract: A non-volatile memory system is provided that includes a plurality of NAND strings of non-volatile storage elements, each non-volatile storage element including a control gate, a tunneling layer, a floating gate, and a blocking layer including a ferroelectric material. The tunneling layer is disposed between the control gate and the floating gate, and the floating gate is disposed between the tunneling layer and the blocking layer.Type: GrantFiled: September 24, 2019Date of Patent: August 4, 2020Assignee: SanDisk Technologies LLCInventors: Yingda Dong, Yangyin Chen, Yukihiro Sakotsubo
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Patent number: 10732847Abstract: A non-volatile memory system may include a non-volatile memory die storing a requested data set that a host requests to be read. In response to the host request, a copy of a data set may be retrieved from the non-volatile memory die without performing error correction on an entry identifying a physical address where the data set is stored. If the data set copy matches the requested data set, the data set copy may be sent to the host. If the data set copy does not match the requested data set, then error correction may be performed on a copy of the entry to identify the correct physical address where the requested data set is stored. A copy of the requested data set may then be retrieved and sent to the host.Type: GrantFiled: January 30, 2019Date of Patent: August 4, 2020Assignee: SanDisk Technologies LLCInventors: Alexander Bazarsky, Grishma Shah, Idan Alrod, Eran Sharon
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Publication number: 20200243138Abstract: Techniques for fast programming and read operations for memory cells. A first set of bit lines is connected to a first set of NAND strings and is interleaved with a second set of bit lines connected to a second set of NAND strings. The first set of NAND strings can be programmed by driving a voltage on the first set of bit lines while floating a voltage on the second set of bit lines, to reduce an inter-bit line capacitance and provide a relatively high access speed and a relatively low storage density (e.g., bits per memory cell). The second set of NAND strings can be programmed by concurrently driving a voltage on the first and second sets of bit lines, to provide a relatively low access speed and a relatively high storage density.Type: ApplicationFiled: April 7, 2020Publication date: July 30, 2020Applicant: SanDisk Technologies LLCInventors: Xiang Yang, Huai-Yuan Tseng, Deepanshu Dutta
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Publication number: 20200243141Abstract: Techniques are provided for optimizing a program operation in a memory device to compensate for program speed variations due to block oxide thinning. In one approach, during a program operation, a program voltage which indicates program speed is acquired from sub-blocks with the highest and lowest program speeds. An initial program voltage for intermediate sub-blocks can be determined based on the acquired program voltages and the positions of the intermediate sub-blocks. The technique can accommodate a loss of one or both acquired program voltages if the programming is interrupted. In another approach, a program voltage which indicates program speed is acquired from one sub-block, and for a later-programmed sub-block, an appropriate offset is located from a table and summed with the acquired program voltage to determine an optimum initial program voltage.Type: ApplicationFiled: April 13, 2020Publication date: July 30, 2020Applicant: SanDisk Technologies LLCInventors: Ching-Huang Lu, Ashish Baraskar, Vinh Diep
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Publication number: 20200243147Abstract: Techniques are provided to compensate for neighbor word line interference when programming memory cells connected to a selected word line WLn. Before programming, the assigned data states of WLn and WLn+1 are compared and corresponding compensation data is generated. The compensation data may be stored in latches of sense circuits to modify the verify tests which occur during programming. The compensation can involve adjusting the bit line voltage, word line voltage, sense node discharge period and/or trip voltage. During a verify test, the compensation data can cause a WLn memory cell to complete programming when its threshold voltage is lower than would be the case with no compensation. When the WLn+1 memory cells are subsequently programmed, an upshift in the threshold voltage of the WLn memory cell offsets the compensation.Type: ApplicationFiled: January 25, 2019Publication date: July 30, 2020Applicant: SanDisk Technologies LLCInventor: Xiang Yang
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Patent number: 10726940Abstract: Apparatuses, systems, and methods are disclosed for skip inconsistency correction. A skip circuit is configured to skip memory units for read operations and write operations of a memory array, based on a record of memory units identified as faulty. A skip inconsistency detection circuit is configured to detect a skip inconsistency in read data from a memory array. A correction circuit is configured to correct a skip inconsistency and output corrected read data.Type: GrantFiled: January 3, 2019Date of Patent: July 28, 2020Assignee: SanDisk Technologies LLCInventors: Zhuojie Li, Hua-Ling Cynthia Hsu, Yen-Lung Li, Min Peng
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Patent number: 10725699Abstract: An apparatus is provided that includes a processor and an instruction memory including a first memory, a second memory, a third memory and an instruction selector circuit. The first memory is configured to receive a first instruction address from the processor, the second memory is configured to receive the first instruction address from the processor and generate a control signal based on the received first instruction address, and the third memory is configured to receive the first instruction address from the processor. The instruction selector circuit is configured to selectively send an instruction from one of the first memory and the third memory based on the control signal to the processor, and to selectively enable and disable the third memory to reduce power consumption of the instruction memory.Type: GrantFiled: June 22, 2018Date of Patent: July 28, 2020Assignee: SanDisk Technologies LLCInventors: Chi-Lin Hsu, Tai-Yuan Tseng, Yan Li, Hiroyuki Mizukoshi
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Patent number: 10725860Abstract: A storage system and method for handling a burst of errors is provided. In one embodiment, the method comprises generating a protograph using an error code generation method; generating a first partially-lifted protograph based on the generated protograph that avoids a first burst of errors; generating a fully-lifted protograph based on the generated protograph and the generated first partially-lifted protograph; and providing the fully-lifted protograph to a storage system comprising a memory.Type: GrantFiled: May 1, 2018Date of Patent: July 28, 2020Assignee: SanDisk Technologies LLCInventors: David Avraham, Ran Zamir, Eran Sharon
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Patent number: 10725104Abstract: Disclosed is an apparatus including a datapath and a test circuit. The datapath is configured to transfer data between a memory core and an IO interface. The datapath includes a plurality of circuits, and a memory core interface. The plurality of circuits operates according to a supply voltage. The test circuit is coupled to the datapath, and configured to determine, from a set of operable voltage levels of the supply voltage, a first minimum operable voltage level for the datapath to operate for the data traversing the datapath at a first frequency.Type: GrantFiled: December 22, 2017Date of Patent: July 28, 2020Assignee: SanDisk Technologies LLCInventors: Amandeep Kaur, Sridhar Yadala, Jayanth Mysore Thimmaiah, Ravindra Arjun Madpur
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Patent number: 10726920Abstract: Techniques are provided for pre-charging NAND strings during a programming operation. The NAND strings are in a block that is divided into vertical sub-blocks. During a pre-charge phase of a programming operation, an overdrive voltage is applied to some memory cells and a bypass voltage is applied to other memory cells. The overdrive voltage allows the channel of an unselected NAND string to adequately charge during the pre-charge phase. Adequate charging of the channel helps the channel voltage to boost to a sufficient level to inhibit programming of an unselected memory cell during a program phase. Thus, program disturb is prevented, or at least reduced. The technique allows, for example, programming of memory cells in a middle vertical sub-block without causing program disturb of memory cells that are not to receive programming.Type: GrantFiled: November 26, 2018Date of Patent: July 28, 2020Assignee: SanDisk Technologies LLCInventor: Xiang Yang
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Patent number: 10726189Abstract: A static timing analysis controller includes a feedback loop identification module that identifies invariable flip flop feedback loops of an integrated circuit design, and adds the identified feedback loops to false path lists. The static timing analysis controller then performs timing update operations and identifies hold violations based on the invariable flip flop feedback loops included in the false path list. In turn, the static timing analysis controller identifies reduced or less pessimistic numbers of hold violations, resulting in fewer buffers added to the integrated circuit design.Type: GrantFiled: July 23, 2018Date of Patent: July 28, 2020Assignee: SanDisk Technologies LLCInventors: Norihiro Kamae, Minoru Yamashita, Biju Manuel
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Patent number: 10726923Abstract: Systems and methods reduce latency during read-verify and programming operations by biasing a dummy line next to a neighboring bit line with an over-drive voltage during a first period and then biasing the dummy line to a same voltage as that of the neighboring bit line during a second period that contiguously follows the first period. The dummy line may be biased based on a state of the neighboring bit line. For example, a first dummy line is first charged to an over-drive voltage and then charged to the same voltage as that of a first neighboring bit line, and a second dummy line at an opposing edge is first charged to the over-drive voltage and then charged to the same voltage as that of a second neighboring bit line. This biasing scheme using the dummy lines helps reduce capacitive loading for neighboring bit lines during ready-verify and programming operations.Type: GrantFiled: November 21, 2018Date of Patent: July 28, 2020Assignee: SanDisk Technologies LLCInventor: Xiang Yang
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Patent number: 10726922Abstract: Apparatuses and techniques for fast programming and read operations for memory cells. A group of word lines comprising a selected word line and one or more adjacent word lines are driven with a common voltage signal during program and read operations. The word lines may be permanently connected to one another or connected by a switch. In another approach, the word lines are driven separately by common voltage signals. In a set of blocks, one block of memory cells can be provided with connected word lines to provide a relatively high access speed, while another block of memory cells has disconnected word lines to provide a higher storage density. In another aspect, the memory cells of a word line are divided into portions, and a portion which is closest to a row decoder is reserved for high access speed with a low storage density.Type: GrantFiled: June 5, 2018Date of Patent: July 28, 2020Assignee: SanDisk Technologies LLCInventors: Xiang Yang, Huai-Yuan Tseng, Deepanshu Dutta
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Patent number: 10727825Abstract: A circuit system may include a first stage circuit configured to generate two pairs of signals in response to an input signal. The circuit system may also include a second stage circuit that is configured to combine a first signal of a first pair with a first signal of a second pair to generate a first combined signal, and to combine a second signal of the first pair with a second signal of the second pair to generate a second combined signal. Transistors of the second stage circuit may be sized in relation to transition timings of the first and second pairs of signals such that skew and duty cycle distortion is minimized between the first and second combined signals.Type: GrantFiled: June 19, 2017Date of Patent: July 28, 2020Assignee: SanDisk Technologies LLCInventor: Shiv Harit Mathur
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Patent number: 10726929Abstract: Techniques are provided to compensate for neighbor word line interference when programming memory cells connected to a selected word line WLn. Before programming, the assigned data states of WLn and WLn+1 are compared and corresponding compensation data is generated. The compensation data may be stored in latches of sense circuits to modify the verify tests which occur during programming. The compensation can involve adjusting the bit line voltage, word line voltage, sense node discharge period and/or trip voltage. During a verify test, the compensation data can cause a WLn memory cell to complete programming when its threshold voltage is lower than would be the case with no compensation. When the WLn+1 memory cells are subsequently programmed, an upshift in the threshold voltage of the WLn memory cell offsets the compensation.Type: GrantFiled: January 25, 2019Date of Patent: July 28, 2020Assignee: SanDisk Technologies LLCInventor: Xiang Yang
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Patent number: 10725677Abstract: A memory device may be configured to leverage memory resources of a host computing device to efficiently transition between different power states. In some embodiments, the memory device stores resume data within a host memory buffer (HMB) before transitioning to a low-power state, and uses the resume data stored within the HMB to resume operation from the low-power state. The memory device may be configured to pre-populate the HMB with resume data prior to transitioning to the low-power state. In some embodiments, the disclosed memory device is configured to gradually resume from the low-power state, which may comprise resuming services of the memory device in the order such services are required during the resume process.Type: GrantFiled: December 19, 2017Date of Patent: July 28, 2020Assignee: SanDisk Technologies LLCInventors: Noga Harari Shechter, Shay Benisty, Judah Gamliel Hahn, Yair Baram
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Patent number: 10726921Abstract: A three-dimensional block includes a stack comprising a plurality of control gate layers configured to bias memory cells of the block. The block includes a plurality of track regions that includes three or more hookup regions. The plurality of track regions separate the memory cells into three memory cell regions. Tracks extending in the track regions supply voltages to the hookup regions. A system includes a memory plane of blocks, and a plurality of track regions, each extending across the memory plane of blocks.Type: GrantFiled: March 30, 2018Date of Patent: July 28, 2020Assignee: SanDisk Technologies LLCInventors: Chia-Lin Hsiung, Fumiaki Toyama, Tai-Yuan Tseng, Yan Li
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Patent number: 10726910Abstract: Disclosed is a device including a sinking circuit to sink current from an output node and a driver circuit coupled to the sinking circuit. The driver circuit includes complementary differential pairs to receive a voltage at the output node and generate a control signal according to the received voltage. The sinking circuit is configured to change the current from the output node according to the control signal.Type: GrantFiled: January 18, 2018Date of Patent: July 28, 2020Assignee: SanDisk Technologies LLCInventors: Albert Chang, Khin Htoo, Matt Chen
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Publication number: 20200234768Abstract: Techniques are provided for predictively programming of non-volatile memory, which may reduce the number of verify operations. In one aspect, a programming circuit is configured to program memory cells to a verify low voltage and to program a set of the memory cells to target states. The set comprises memory cells having a threshold voltage between the verify low voltage and a verify high voltage. To program the set of the memory cells to the target states, the programming circuit is configured to apply two or more program pulses to memory cells in the set without verifying whether the memory cells have reached their respective target states, including: apply a first and second program enable voltages to the bit lines associated with the memory cells having different strengths.Type: ApplicationFiled: February 22, 2019Publication date: July 23, 2020Applicant: SanDisk Technologies LLCInventors: Lei Lin, Zhuojie Li, Tai-Yuan Tseng, Henry Chin, Gerrit Jan Hemink
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Publication number: 20200227125Abstract: An apparatus includes a programming circuit configured to supply a program pulse to increase a threshold voltage of a memory cell. The apparatus also includes a sensing circuit configured to determine that the threshold voltage of the memory cell satisfies a trigger threshold voltage in response to the program pulse. The apparatus further includes a damping circuit configured to increase a voltage of a bit line connected to the memory cell after initiation of and during a second program pulse in response to the threshold voltage of the memory cell satisfying the trigger threshold voltage, the second program pulse being sent by the programming circuit.Type: ApplicationFiled: March 25, 2020Publication date: July 16, 2020Applicant: SanDisk Technologies LLCInventors: Xiang Yang, Deepanshu Dutta, Gerrit Jan Hemink, Tai-Yuan Tseng, Yan Li
