Patents Assigned to SanDisk Technologies LLC
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Patent number: 10580504Abstract: Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.Type: GrantFiled: June 7, 2018Date of Patent: March 3, 2020Assignee: SanDisk Technologies LLCInventors: Dengtao Zhao, Peng Zhang, Nan Lu, Deepanshu Dutta
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Patent number: 10573395Abstract: Non-volatile memory strings, which are coupled to respective bit lines and source lines, may include multiple non-volatile memory cells coupled to respective word lines. Multiple sensing operations may be used to determine data programmed into a particular non-volatile memory cell. For example, a control circuit may sense multiple values from a particular non-volatile memory cell included in a non-volatile memory string using different voltage levels on a source line coupled to the non-volatile memory string. The control circuit may select one of the multiple values based on a program state of a different non-volatile memory cell adjacent to the particular non-volatile memory cell.Type: GrantFiled: November 30, 2018Date of Patent: February 25, 2020Assignee: SanDisk Technologies LLCInventors: Xiang Yang, Gerrit Jan Hemink
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Method and system for visualizing a correlation between host commands and storage system performance
Patent number: 10564888Abstract: A method and system for visualizing a correlation between host commands and storage system performance are provided. In one embodiment, a method comprises receiving information concerning host operations of a host performed over a time period; receiving information concerning storage system operations of a storage system performed over the time period; and simultaneously displaying both the host operations and the storage system operations over the time period. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.Type: GrantFiled: April 1, 2019Date of Patent: February 18, 2020Assignee: SanDisk Technologies LLCInventors: Tal Shaked, Omer Gilad, Liat Hod, Eyal Sobol, Einav Zilberstein, Judah Gamliel Hahn -
Patent number: 10567006Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured, during execution of a relocation operation that includes storage of data to a memory buffer of an access device and retrieval of the data including data bits and first error correction code (ECC) parity bits from the memory buffer, to generate second ECC parity bits based on the data bits from the memory buffer and to compare the first ECC parity bits to the second ECC parity bits.Type: GrantFiled: August 5, 2016Date of Patent: February 18, 2020Assignee: Sandisk Technologies LLCInventors: Judah Gamliel Hahn, Igor Genshaft, Marina Frid
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Publication number: 20200051648Abstract: Program disturb is a condition that includes the unintended programming while performing a programming process for memory cells, where the program disturb can affect both memory cells and select gates in a NAND structure. During a pre-charge phase of a programming operation, a drain side select gate may be biased to a higher voltage than an adjacent word line, resulting in a disturb of the select gate due to hot-electron injection. This can raise the threshold voltage of the select gate, causing error in reading the NAND string or even making it inaccessible. To help avoid this problem, during a program pre-charge, the voltage applied to the select gate is raised in a sequence of steps, rather than driving the select gate directly to its final pre-charge voltage level.Type: ApplicationFiled: August 7, 2018Publication date: February 13, 2020Applicant: SanDisk Technologies LLCInventor: Xiang Yang
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Patent number: 10559365Abstract: An apparatus includes a plurality of solid-state storage elements, a plurality of control lines coupled to the plurality of solid-state storage elements, and control circuitry in communication with the plurality of control lines. The control circuitry is configured to during a first phase of a control line pre-charging stage, charge one or more unselected control lines of the plurality of control lines using a regulated charging current for a period of time based at least in part on a bias variance state associated with the plurality of control lines, and during a second phase of the control line pre-charging stage, charge the one or more unselected bit lines to an inhibit voltage level using an unregulated charging current.Type: GrantFiled: March 27, 2018Date of Patent: February 11, 2020Assignee: SanDisk Technologies LLCInventors: Xiang Yang, Huai-yuan Tseng, Deepanshu Dutta
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Patent number: 10558381Abstract: Apparatuses, systems, methods, and computer program products are disclosed for dynamic read table generation. One apparatus includes a set of non-volatile storage cells. A controller for a set of non-volatile storage cells is configured to, in response to unsuccessfully reading a storage cell of the set of non-volatile storage cells using a parameter, read the storage cell using one or more shifted values. A controller for a set of non-volatile storage cells is configured to, in response to successfully reading a storage cell using one or more shifted values, add the one or more shifted values to a storage device.Type: GrantFiled: December 16, 2016Date of Patent: February 11, 2020Assignee: SanDisk Technologies LLCInventors: Henry Chin, Sateesh Desireddi, Dana Lee, Ashwin D T, Harshul Gupta, Parth Amin, Jia Li
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Patent number: 10559368Abstract: Program disturb is a condition that includes the unintended programming while performing a programming process for memory cells, where the program disturb can affect both memory cells and select gates in a NAND structure. During a pre-charge phase of a programming operation, a drain side select gate may be biased to a higher voltage than an adjacent word line, resulting in a disturb of the select gate due to hot-electron injection. This can raise the threshold voltage of the select gate, causing error in reading the NAND string or even making it inaccessible. To help avoid this problem, during a program pre-charge, the voltage applied to the select gate is raised in a sequence of steps, rather than driving the select gate directly to its final pre-charge voltage level.Type: GrantFiled: August 7, 2018Date of Patent: February 11, 2020Assignee: SanDisk Technologies LLCInventor: Xiang Yang
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Patent number: 10553301Abstract: Non-volatile memory and processes for reprogramming data posing a potential reliability concern are provided. A process is provided for distinguishing between cross-temperature effects and read disturb effects as part of determining whether to perform a maintenance operation such as reprogramming. A process is provided that compensates for cross-temperature effects while testing to determine whether to perform a maintenance operation. Applying temperature compensation attempts to remove cross-temperature effects so that testing accurately detects whether read disturb has occurred, without the effects of temperature. By reducing cross-temperature effects, maintenance operations can be more accurately scheduled for memory that has experienced read disturb, as opposed to cross-temperature effects.Type: GrantFiled: August 15, 2017Date of Patent: February 4, 2020Assignee: SanDisk Technologies LLCInventors: Narayan K, Sateesh Desireddi, Aneesh Puthoor, Dharmaraju Marenahally Krishna, Arun Thandapani, Divya Prasad, Thendral Murugaiyan, Piyush Dhotre
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Patent number: 10553647Abstract: An apparatus is provided that includes a bit line above a substrate, a word line above the substrate, and a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a reversible resistance-switching memory element coupled in series with an isolation element. The isolation element includes a first selector element coupled in series with a second selector element. The first selector element includes a first snapback current, and the second selector element includes a second snapback current lower than the first snapback current.Type: GrantFiled: June 28, 2018Date of Patent: February 4, 2020Assignee: SanDisk Technologies LLCInventors: Michael K. Grobis, Derek Stewart, Bruce D. Terris
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Publication number: 20200034686Abstract: Use of a non-volatile memory array architecture to realize a neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a neural network is formed by a differential memory cell of two individual memory cells, such as a memory cells having a programmable resistance, each connected between a corresponding one of a word line pair and a shared bit line. An input is applied as a pattern of voltage values on word line pairs connected to the unit synapses to perform the multiplication of the input with the weight by determining a voltage level on the shared bit line. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a summation circuit.Type: ApplicationFiled: May 7, 2019Publication date: January 30, 2020Applicant: SanDisk Technologies LLCInventors: Pi-Feng Chiu, Won Ho Choi, Wen Ma, Martin Lueker-Boden
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Publication number: 20200034697Abstract: Use of a NAND array architecture to realize a binary neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a BNN is stored in a pair of series connected memory cells. A binary input is applied as a pattern of voltage values on a pair of word lines connected to the unit synapse to perform the multiplication of the input with the weight by determining whether or not the unit synapse conducts. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a counter.Type: ApplicationFiled: March 28, 2019Publication date: January 30, 2020Applicant: SanDisk Technologies LLCInventors: Won Ho Choi, Pi-Feng Chiu, Wen Ma, Minghai Qin, Gerrit Jan Hemink, Martin Lueker-Boden
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Publication number: 20200035305Abstract: Use of a non-volatile memory array architecture to realize a neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a neural network is formed by a differential memory cell of two individual memory cells, such as a memory cells having a programmable resistance, each connected between a corresponding one of a word line pair and a shared bit line. An input is applied as a pattern of voltage values on word line pairs connected to the unit synapses to perform the multiplication of the input with the weight by determining a voltage level on the shared bit line. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a summation circuit. The approach can be extended from binary weights to multi-bit weight values by use of multiple differential memory cells for a weight.Type: ApplicationFiled: May 16, 2019Publication date: January 30, 2020Applicant: SanDisk Technologies LLCInventors: Won Ho Choi, Pi-Feng Chiu, Wen Ma, Martin Lueker-Boden
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Patent number: 10546647Abstract: An oscillator circuit includes a voltage controlled oscillator (VCO) configured to generate a clock signal having a clock period that is adjustable based on a control signal. The oscillator circuit includes a time to voltage converter configured to receive the clock signal and generate a compensation voltage potential that is proportional to the clock period and a zero temperature coefficient (ZTC) current. The oscillator circuit includes an amplifier configured to generate the control signal responsive to the compensation voltage potential and a temperature independent reference voltage potential. A method includes applying a control signal to a VCO, generating a clock signal having a clock period responsive to the control signal, generating a compensation voltage potential, and adjusting the clock period using the compensation voltage potential. A memory device includes the oscillator circuit.Type: GrantFiled: June 26, 2017Date of Patent: January 28, 2020Assignee: Sandisk Technologies LLCInventors: Deep Saxena, Saurabh Kumar Singh
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Patent number: 10545692Abstract: Apparatuses, systems, methods, and computer program products are disclosed for memory maintenance operations. A non-volatile memory device comprises a non-volatile memory medium. A non-volatile memory device is configured to receive a refresh command from a controller over a bus. A non-volatile memory device is configured to perform one or more maintenance operations on a non-volatile memory medium during a predefined period of time after receiving a refresh command.Type: GrantFiled: April 4, 2018Date of Patent: January 28, 2020Assignee: SanDisk Technologies LLCInventors: Nathan Franklin, Ward Parkinson
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Patent number: 10545678Abstract: A shared storage system includes a plurality of storage processors. A first storage processor of the plurality of storage processors is coupled with a shared storage device having a plurality of storage devices. The first storage processor receives a first verify connectivity request from an initiator device. In response to the first verify connectivity request, the first storage processor transmits a first ready response to the initiator device. After transmitting the first ready response, the first storage processor detects that the first storage processor is decoupled from the shared storage device. In accordance with detecting that the first storage processor is decoupled from the shared storage device, the first storage processor transmits a not-ready response to the initiator device in response to a second verify connectivity request from the initiator device.Type: GrantFiled: April 19, 2017Date of Patent: January 28, 2020Assignee: SanDisk Technologies LLCInventors: Bart Joris A. Van Assche, Mark Ruijter
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Patent number: 10546870Abstract: A three-dimensional NAND memory string includes an alternating stack of insulating layers and word line layers extending in a word line direction, a memory array region in the alternating stack containing memory stack structures, a group of more than two column stairs located in the alternating stack and extending in the word line direction from one side of the memory array region, and bit lines electrically contacting the vertical semiconductor channels and extending in a bit line direction which is perpendicular to the word line direction. Each column stair of the group of N column stairs has a respective step in a first vertical plane which extends in the bit line direction, and the respective steps in the first vertical plane decrease and then increase from one end column stair to another end column stair.Type: GrantFiled: April 18, 2018Date of Patent: January 28, 2020Assignee: SanDisk Technologies LLCInventors: Seiji Shimabukuro, Kensuke Yamaguchi
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Publication number: 20200026818Abstract: A static timing analysis controller includes a feedback loop identification module that identifies invariable flip flop feedback loops of an integrated circuit design, and adds the identified feedback loops to false path lists. The static timing analysis controller then performs timing update operations and identifies hold violations based on the invariable flip flop feedback loops included in the false path list. In turn, the static timing analysis controller identifies reduced or less pessimistic numbers of hold violations, resulting in fewer buffers added to the integrated circuit design.Type: ApplicationFiled: July 23, 2018Publication date: January 23, 2020Applicant: SanDisk Technologies LLCInventors: Norihiro Kamae, Minoru Yamashita, Biju Manuel
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Patent number: 10541037Abstract: Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.Type: GrantFiled: June 7, 2018Date of Patent: January 21, 2020Assignee: SanDisk Technologies LLCInventors: Dengtao Zhao, Deepanshu Dutta
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Patent number: 10541035Abstract: Apparatuses and techniques are provided for accurately reading memory cells by compensating for lateral charge diffusion between adjacent memory cells. A selected memory cell is read with a compensation which is based on classifying the threshold voltages of adjacent memory cells into bins. In one aspect, the compensation is based on the level of the current control gate voltage of the selected word line. In another aspect, the classifying of the threshold voltages of the adjacent memory cells can be a function of temperature. In another aspect, a memory cell can be read with compensation after a previous read operation without compensation results in an uncorrectable error. In another aspect, the classifying uses more bins for a selected edge word line.Type: GrantFiled: June 28, 2018Date of Patent: January 21, 2020Assignee: SanDisk Technologies LLCInventors: Ching-Huang Lu, Han-Ping Chen, Chung-Yao Pai, Yingda Dong
