Abstract: A device includes a memory a memory configured to store syndromes. The device also includes a pipelined data processing unit and routing circuitry. The routing circuitry includes a first input coupled to the memory and includes a second input coupled to an output of the pipelined data processing unit.

Abstract: A memory device and associated techniques provide a read recovery of data in case of a short circuit between word lines. When cells of a recovery word line WLrec are successfully programmed but cells of an adjacent work line WLrec+1 are not successfully programmed, the data of the cells of WLrec can be recovered. The cells of WLrec+1 are erased so that a low pass voltage on WLrec+1 is adequate to provide these cells in a conductive state during the recovery read of WLrec. Capacitive coupling between the word lines which shifts the apparent threshold voltage of the cells on WLrec is reduced so that a more accurate recovery read can be performed. Read voltages on WLrec can be upshifted compared to baseline read voltages.

Abstract: In one aspect, a voltage is provided as a rectangular waveform in which the duty cycle is varied to provide different effective voltages. These voltages may be applied to various control lines in a memory device such as a word line, bit line and/or source line, in a program, verify, read or erase operation. In some cases, the duty cycle is a function of programming data of a memory cell such as an assigned data state or a programming speed category. The duty cycle could also be a function of a programming phase or other criterion. The duty cycle can be varied by modifying the duration and separation of the pulses of the waveform or by pulse counting, in which a specified number of pulses are passed in a time period.

Abstract: In a non-volatile memory system, a fast bulk secure erase method for erasing data includes, in response to a secure erase command: applying charge to a portion of non-volatile memory in the non-volatile memory system, and performing an erase operation sufficient to remove charge from the portion of non-volatile memory to below an erase threshold. The applied charge is sufficient to program memory cells in the portion of non-volatile memory to above a pre-erase program threshold.

Abstract: Systems and methods for managing programming schedules of programming host data and maintenance operations in a non-volatile memory are disclosed. A method includes determining multiple integer interleave ratios of host data writes to relocation writes of previously programmed data when non-integer interleave situations are determined for a previously programmed source block selected for a maintenance operation. The method may include writing the host data and relocating previously programmed data in groups of operations having these determined integer interleave ratios. A memory system may include non-volatile memory and a controller configured to identify non-integer interleave situations and then break up the host data and relocation data writes into multiple interleave groups each having a different integer interleave ratio such that a whole number of write operations for the interleave groups may be carried out to achieve more precise control and efficiency in maintenance operations.

Abstract: A method of fabricating a monolithic three dimensional memory structure is provided. The method includes forming a stack of alternating word line and dielectric layers above a substrate, forming a source line above the substrate, forming a memory hole extending through the alternating word line and dielectric layers and the source line, and forming a mechanical support element on the substrate adjacent to the memory hole.

Abstract: Disclosed herein are methods of fabricating a source side select (SGS) transistor in 3D memory. The threshold voltage of the SGS transistor accurately meets a target threshold voltage. The SGS transistor has a semiconductor body that resides in a memory hole formed in a stack of alternating layers of two materials. During fabrication, a sacrificial layer may be removed to create recesses between dielectric layers in a stack. The sacrificial layer may be removed by introducing an etchant into slits formed in the stack. Thus, the recess may expose sidewalls of the body of the SGS transistor. An impurity may be introduced into this recess, by way of a slit, in order to dope the source side select transistor. This allows for precise control over the doping profile, which in turn provides for precise control over the threshold voltage of the SGS transistor.

Abstract: A method of forming a shallow trench isolation trench in a semiconductor substrate is described. The method includes forming a trench in a region of the substrate, forming a first dielectric material in the trench, forming a second dielectric material above the first dielectric material, forming a first air gap in the first dielectric material in the trench, and forming a second air gap in the second dielectric material above the first air gap.

Abstract: A non-volatile memory system may include a tracking module that tracks logic values of bits to be stored in memory elements identified as unreliable. A record of the logic values may be generated. During decoding of the data, a log likelihood ratio module may use the record to assign log likelihood ratio values for the decoding.

Abstract: Methods, systems and/or devices are used for limiting write command execution in a storage device comprising a set of non-volatile memory devices. In one aspect, the method includes (1) accessing in a holding queue host-specified write commands specified by a host system, each of the host-specified write commands specifying a number of pages to be written to the set of non-volatile memory devices; (2) in accordance with a determination that throttling is enabled: (3) determining a limit number of pages for a current throttle period in accordance with a throttle rate, the throttle rate being a maximum write rate for executing host-specified write commands; and (4) during the current throttle period, moving from the holding queue to a pending queue, for execution by the set of non-volatile memory devices, host-specified write commands whose total specified number of pages does not exceed the limit number of pages.

Abstract: A solution for combining a portion of data from a block of single level cells to a block of multi-level cells. The solution includes identifying word lines with only valid data and word lines with non-valid data in a selected block of single level cells, copying data from word lines with valid data to a destination block of multi-level cells and copying data from word lines in the selected block of single level cells with non-valid data to a separate compaction block of single level cells. The system includes a first controller module configured to scan for word lines with only valid data and pass a bitmap identifying valid and invalid word lines to a second controller module. The second controller module is configured to perform on-chip combining of data from valid word lines, and copy data from invalid data word lines to a compaction block of single level cells.

Abstract: A NAND memory is provided that includes a memory cell region and a peripheral region. The peripheral region includes a shallow trench isolation trench disposed in a substrate. The shallow trench isolation trench has a first tab extension and a second tab extension. The first tab extension is disposed at a top portion of the shallow trench isolation trench, and extends in a first direction from the shallow trench isolation trench. The second tab extension is disposed at a top portion of the shallow trench isolation trench, and extends in a second direction from the shallow trench isolation trench.

Abstract: A memory controller receives a command to perform a memory operation, the command including a data packet comprising a plurality of data divisions. In response to receiving the command, for each individual memory device, the memory controller assigns to the individual memory device a respective data division, the respective data division including a plurality of data segments, and determines a single relative memory address associated with an address specified by the received command. The memory controller assembles a sub-request comprising a single contiguous instruction portion, which includes the single relative memory address and one or more instructions to perform the memory operation, and the respective data division, the respective data division following the single contiguous instruction portion, and transmits the sub-request to every memory portion of the number of memory portions of the individual memory device.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for hybrid checkpointed memory. An extended memory module uses volatile memory of a host and a non-volatile memory medium as virtual memory for the host. A clone module clones data of a range of virtual memory in response to a checkpoint event for the range of virtual memory. A range of virtual memory may include data stored in a volatile memory and data stored in a non-volatile memory medium. A checkpoint module flushes dirty data of a range of virtual memory to a non-volatile memory medium in response to a checkpoint event. A hybrid checkpointed memory interface provides access to data of a range of virtual memory while dirty data is being flushed using data of a range of virtual memory, or using a clone of the data.

Abstract: A method is provided that includes forming a dielectric material above a substrate, forming a hole in the dielectric material, the hole disposed in a first direction, forming a word line layer above the substrate via the hole, the word line layer disposed in a second direction perpendicular to the first direction, the word line layer including a first conductive material having a first work function, forming a nonvolatile memory material on a sidewall of the hole, the nonvolatile memory material including a semiconductor material layer and a conductive oxide material layer, forming a local bit line in the hole, the local bit line including a second conductive material having a second work function, wherein the first work function is greater than the second work function, and forming a memory cell comprising the nonvolatile memory material at an intersection of the local bit line and the word line layer.

Abstract: A cache and/or storage module may be configured to reduce write amplification in a cache storage. Cache layer write amplification (CLWA) may occur due to an over-permissive admission policy. The cache module may be configured to reduce CLWA by configuring admission policies to avoid unnecessary writes. Admission policies may be predicated on access and/or sequentiality metrics. Flash layer write amplification (FLWA) may arise due to the write-once properties of the storage medium. FLWA may be reduced by delegating cache eviction functionality to the underlying storage layer. The cache and storage layers may be configured to communicate coordination information, which may be leveraged to improve the performance of cache and/or storage operations.

Abstract: A bit scan circuit includes N scan blocks corresponding with an N-bit string of binary data. The string is scanned using an input clock signal to count the number of bits having a predetermined binary value. Each scan block includes a single latch to transfer the corresponding bit and to indicate reset. The scan blocks are organized into groups. Each group is enabled by a corresponding token signal. The token signal for each group is asserted after each preceding scan block indicates a pass value. When enabled by its token signal, the first scan block in a group is reset by a first clock signal. A second scan block in the group is enabled for reset after the first scan block indicates the pass value. The second scan block in the group is reset by a second clock signal having pulses that precede corresponding pulses from the first clock signal.

Abstract: Storage divisions of a non-volatile storage medium may have a writable state and an unwritable state. Storage divisions may be reclaimed by, inter alia, resetting the storage division from an unwritable state to a writable state. Writable storage divisions may be used to service incoming storage requests. If no writable storage divisions are available, requests may stall. One or more storage divisions may be held in a writable state to avoid stall conditions. This, however, may increase the erase dwell time of the storage divisions, which can result in increased wear and reduce the usable life of the storage device. Storage divisions may be prepared for use such that the storage divisions are transitioned to a writable state such that erase dwell time of the storage divisions is reduced, and the storage divisions are available as needed to service incoming requests.

Abstract: The various implementations described herein include systems, methods and/or devices for modifying an error correction format of a respective memory portion of non-volatile memory in a storage device. In one aspect, the method includes, for respective memory portions of the non-volatile memory, obtaining a performance metric of the respective memory portion, and modifying a current error correction format in accordance with the measured performance metric, the current error correction format corresponding to a code rate, codeword structure, and error correction type. Furthermore, data is stored, and errors are detected and corrected, in the respective memory portion in accordance with the modified error correction format. The current and modified error correction formats are distinct, and comprise two of a sequence of predefined error correction formats, wherein a plurality of the sequence of predefined error correction formats have a same number of error correction bits and different numbers of data bits.

Abstract: A decoder includes syndrome storage and a first barrel shifter configured to bit-shift hard decision bit data to generate shifted data that is aligned with a set of syndromes from the syndrome storage. The decoder also includes a first syndrome update circuit coupled to the first barrel shifter and configured to process the set of syndromes based on the shifted data to generate an updated version of the set of syndromes. The decoder may also be configured to perform on-the-fly syndrome weight computation.