Abstract: A method includes generating a first error correcting code (ECC) codeword and a second ECC codeword. The method further includes generating redundancy information based on at least a portion of the first ECC codeword and further based on at least a portion of the second ECC codeword. The method further includes storing the first ECC codeword, the second ECC codeword, and the redundancy information at a word line of a memory of a data storage device.

Abstract: A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends a height of a first tier of the stack and a metal pillar above the polysilicon pillar extends a height of a second tier of the stack.

Abstract: A storage system and method for adaptive thermal throttling are disclosed. In one embodiment, a method for adaptive thermal throttling is provided that is performed in a storage system having a memory. This method comprises determining if a temperature of the storage system is above a threshold temperature; and in response to determining that the temperature of the storage system is above the threshold temperature: reducing performance of the storage system in an iterative manner until the temperature of the storage system is within a temperature envelope around the threshold temperature; and storing, in the memory, a value indicating what the performance of the storage system was reduced to in order to get the temperature within the temperature envelope. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A memory device and associated techniques for reducing read disturb of memory cells during the last phase of a sensing operation when all voltage signals are ramped down to a steady state voltage. In one aspect, the voltages of the source side word line, WL0, and an adjacent dummy word line, WLDS1, are ramped down after the voltages of remaining word lines are ramped down. This can occur regardless of whether WL0 is the selected word line which is programmed or read. The technique can be applied after the sensing which occurs in a read or program-verify operation. Another option involves elevating the voltage of the selected word line so that all word lines are ramped down from the same level, such as a read pass level. The techniques are particularly useful when the memory device includes an interface in the channel between epitaxial silicon and polysilicon.

Abstract: A method and system for accessing enhanced functionality on a storage device is disclosed. A hijack command is sent to the storage device that includes an identifier (such as a signature or an address). The storage device determines whether to hijack one or more subsequently commands by analyzing the subsequently commands using the identifier. For example, the storage device may analyze the subsequently received commands to determine whether the signature is in the payload of the subsequently received commands. As another example, the storage device may compare the address in the subsequently received commands with the address in the hijack command to determine whether to hijack the subsequently received commands.

Abstract: Disclosed herein is 3D memory with vertical NAND strings having a III-V compound channel, as well as methods of fabrication. The III-V compound has at least one group III element and at least one group V element. The III-V compound provides for high electron mobility transistor cells. Note that III-V materials may have a much higher electron mobility compared to silicon. Thus, much higher cell current and overall cell performance can be achieved. Also, the memory device may have better read-write efficiency due to much higher carrier mobility and velocity. The tunnel dielectric of the memory cells may have an Al2O3 film in direct contact with the III-V NAND channel. The drain end of the NAND channel may be a metal-III-V alloy in direct contact with a metal region. The body of the source side select transistor could be formed from the III-V compound or from crystalline silicon.

Abstract: An array of non-volatile memory cells includes a first plurality of nonvolatile memory cells and a second plurality of non-volatile memory cells. The first plurality of memory cells, which have first diameters of memory holes, are assigned to store portions of data that are not frequently read. The second plurality of memory cells, which have second diameters of memory holes, are assigned to store portions of data that are frequently read. The first diameters are smaller than the second diameters.

Abstract: A non-volatile memory system may be configured to generate a codeword with first-type parity bits and one or more second-type parity bits. If a storage location in which the codeword is to be stored includes one or more bad memory cells, the bit sequence of the codeword may be arranged so that at least some of the second-type parity bits are stored in the bad memory cells. During decoding, a first set of syndrome values may be determined for a first set of check nodes and a second set of syndrome values may be determined for a second set of check nodes. In some examples, a syndrome weight used for determining if convergence is achieved may be calculated using check nodes that are unassociated with the second-type parity bits.

Abstract: A design flow of an integrated circuit may include a skeleton input/output (I/O) generation stage during which information about ESD protection circuitry and rails but not functional circuitry of the I/O cells of the integrated circuit is generated. The information may be used in an ESD analysis stage to generate performance characteristics of the ESD protection circuitry. Results of the ESD analysis may then be used to design optimized ESD protection circuitry along with the rest of the circuit components of the I/O cells. In this way, the design of ESD protection circuitry may be optimized without having to redo a completed I/O cell design and significantly delay the design flow before tapeout.

Abstract: A temperature sensor is disclosed. In one aspect, the temperature sensor provides a digital output having a precise degree/code step. For example, each step in the digital output code may correspond to one degree Celsius. In one aspect, a temperature sensor comprises a precision band-gap circuit and a sigma delta modulator (SDM) analog-to-digital convertor (ADC). A bandgap voltage and a PTAT voltage may be provided from the band-gap circuit as an input to the SDM ADC. The SDM ADC may produce an output based on the difference between the PTAT voltage and the bandgap voltage. The temperature sensor may also have logic that outputs a temperature code based on the output of the SDM ADC.

Abstract: In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.

Abstract: A three-dimensional NAND stacked non-volatile memory array and a DRAM memory array are provided. The three-dimensional NAND stacked non-volatile memory array and the DRAM memory array are integrated on a single substrate.

Abstract: A pipeline system may adjust clock rates of variable-rate clock signals sent to different processing circuit blocks in a pipeline based on their respective, individual input and output buffer fill levels and processor busy statuses. Variable-rate clock generation circuitry may generate the variable-rate clock signals based on a common clock signal. Additionally, the variable-rate clock generation circuitry may set or adjust the rates of variable-rate clock signals linearly in evenly-spaced increments and decrements.

Abstract: Systems, methods and/or devices are used to enable tracking intermix of writes and un-map commands across power cycles. In one aspect, the method includes (1) receiving, at a storage device, a plurality of commands from a host, the storage device including non-volatile memory, (2) maintaining a log corresponding to write commands and un-map commands from the host, (3) maintaining a mapping table in volatile memory, the mapping table used to translate logical addresses to physical addresses, (4) saving the mapping table, on a scheduled basis that is independent of the un-map commands, to the non-volatile memory of the storage device, (5) saving the log to the non-volatile memory, and (6) upon power up of the storage device, rebuilding the mapping table from the saved mapping table in the non-volatile memory of the storage device and from the saved log in the non-volatile memory of the storage device.

Abstract: A voltage regulator circuit is provided in which voltage overshoots are quickly dissipated using a discharge path which is connected to an output of the voltage regulator. Circuitry for controlling the discharge path is provided using internal currents of an error amplifier to provide a space-efficient and power-efficient design with a fast response. Moreover, hysteresis can be provided to avoid toggling between discharge and no discharge, and to avoid undershoot when discharging the output. A digital or analog signal is set which turns the discharge transistor on or off. A current pulldown may be arranged in the discharge path.

Abstract: Systems, methods, and/or devices are used to manage high-priority NAND operations. In some embodiments, the method includes receiving a first command (e.g., requesting a high-priority memory operation) corresponding to a first location (e.g., having both a first physical address and a first aliased physical address) in a first die of a plurality of physical non-volatile memory die in a storage device. If the first die is performing a blocking low-priority memory operation (e.g., the low-priority operation was sent to the first die using a second physical address), the method includes sending a memory operation command, corresponding to the first memory operation, to the first die using the first aliased physical address. In some embodiments, a predefined die-selection portion of the second physical address matches the predefined die-selection portion of the first physical address and does not match the predefined die-selection portion of the first aliased physical address.

Abstract: A storage device with a charge trapping (CT) based memory may include improved data retention (DR) performance. The CT memory may be 3D memory that uses a charge storage layer for storing charge may have unique data retention behavior. Memory blocks using a charge storage layer may be dynamically detected and reconditioned and re-programmed to improve memory characteristics, such as data retention. The reconditioning may include a dedicated erase cycle for a block that improves the data retention.

Abstract: A method is provided that includes forming a transistor by forming a gate disposed in a first direction above a substrate, the gate including a first bridge portion and a second bridge portion, forming the first bridge portion extending in the first direction and disposed near a top of the gate, and forming the second bridge portion extending in the first direction and disposed near a bottom of the gate.