Abstract: An apparatus includes a control circuit configured connect to non-volatile memory cells. The control circuit is configured to receive a read command directed to data stored in non-volatile memory cells of a first word line and determine that a second word line adjacent to the first word line is sanitized. The control circuit is further configured to select an adjusted read voltage for a read operation directed to the non-volatile memory cells of the first word line based on the determination.

Abstract: A data storage device and method for host-determined proactive block clearance are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to receive a command from a host that specifies a parameter of an upcoming burst mode; and in response to receiving the command, proactively perform a garbage collection operation according to the parameter to create available storage space in the memory to store data from the host during the upcoming burst mode. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings and support openings are formed through the alternating stack. The memory openings are arranged in a first hexagonal array having a nearest-neighbor direction that is parallel to a first horizontal direction, and the support openings are arranged in a second hexagonal array having a nearest-neighbor direction that is perpendicular to the first horizontal direction. Memory opening fill structures are formed within a respective one of the memory openings, and support pillar structures within a respective one of the support openings.

Abstract: A data storage device and method are provided for predictable low-latency in a time-sensitive environment. In one embodiment, a data storage device is provided comprising a memory and a controller configured to communicate with the memory. The controller is further configured to: receive, from a host, an indication of a logical block address range that the host will later read; and in response to receiving the indication: read data from the logical block address range; and perform an action on the data to reduce a read latency when the host later reads the logical block address range. Other embodiments are disclosed.

Abstract: A three-dimensional memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers, a second-tier alternating stack of second insulating layers and second electrically conductive layers, a vertically alternating sequence of insulating plates and dielectric material plates laterally surrounded by the second-tier alternating stack, memory openings vertically extending through each layer within the first-tier alternating stack and the second-tier alternating stack, memory opening fill structures located in the memory openings, first contact via structures vertically extending through the vertically alternating sequence and contacting a respective one of the first electrically conductive layers, and second contact via structures contacting a respective one of the second electrically conductive layers.

Abstract: In some exception flows, a device controller may need to store and subsequently recover a current state of a host queue. In these particular exception flows, recovering the current state of the host queue is complex due to the varying states a host queue may be in at the time of storing, including having pending commands in the host queue. Examples of such exception flows include low power modes in client SSDs and live migrations in enterprise SSDs. Using dummy host submission and completion queues during the host queue recovery process allows the device controller to efficiently operate even when there are pending commands in the host queue. The dummy queues may be stored in the HMB, internal DRAM, or any other system dummy buffer (i.e., in a different device or tenant).

Abstract: A data storage device has a cache and a non-volatile memory. Instead of flushing the entire cache to the non-volatile memory in response to a command from a host, the data storage device flushes only the cached data that is associated with an identifier provided by the host. This allows the cached data associated with the identifier to be flushed more quickly. The data storage device can also prioritize queued commands that are associated with the identifier.

Abstract: A data storage device and method for enhanced recovery through data storage device discrete-component-hardware-reset are provided. In one embodiment, the data storage device determines that a subset of a plurality of memory dies is non-responsive, sends a request to a host to accept longer delays associated with the subset of the plurality of memory dies, power-cycles the subset of the plurality of memory dies, and then informs the host that the latency associated with those dies has been restored to normal latency or that the subset of the plurality of memory dies are inactive (in case of unsuccessful recovery). Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A data storage device and method for reducing read disturbs when reading redundantly-stored data are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The memory is configured to redundantly store a plurality of copies of data, wherein the plurality of copies of the data comprise a primary copy of the data and at least one secondary copy of the data. The controller is configured to randomly select one of the plurality of copies of the data instead of selecting the primary copy of the data as a default; and read, from the memory, the randomly-selected one of the plurality of copies of the data. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A data storage device includes a memory device, a random access memory (RAM) device, and a controller coupled to the memory device and the RAM device. The controller is configured to determine a workload type of the data storage device, determine to store at least a portion of a compressed logical to physical translation table (ZCAT) in the RAM device based on the workload type, and utilize a remaining portion of the RAM device to perform background operations. The controller is further configured to determine a persistence or temperature of the ZCAT, where the portion of the ZCAT stored to the RAM device is based on the persistence and/or the temperature of the ZCAT. The remaining portion of the ZCAT is stored in the HMB, where the remaining portion may update any out-of-date ZCAT entries.

Abstract: An alternating stack of first material layers and second material layers is formed over a substrate. A hard mask layer is formed over the alternating stack and cavities are formed in the hard mask layer. A cladding liner is formed on sidewalls of the cavities in the hard mask layer. Via openings are formed through each layer within the alternating stack by performing an anisotropic etch process that transfers a pattern of the cavities through the alternating stack.

Abstract: A data storage device and method are provided for selecting a data recovery mechanism based on a video frame position. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to retrieve a video frame stored in the memory; detect an error in the video frame; and select how to handle the error based on a position of the video frame in a group of pictures. Other embodiments are provided.

Abstract: In a non-volatile memory system that initially writes data in a binary format and then folds the stored data into a multi-level format, transfers of host data from the memory controller to the memory dies of the system are performed during both foggy and fine phases of the multi-level programming as data latches are released, allowing the transfer times to be hidden behind the programming. To improve data throughput one sub-set of the memory dies perform their foggy phase programming while another sub-set of the memory dies perform their fine phase programming, resulting in non-overlapping transfer windows for host data transfers for the two sub-sets of memory dies.

Abstract: Methods for recording commands in memory and providing the recorded commands. In one embodiment, a data storage controller includes a memory interface configured to interface with a memory, a controller memory including a storage firmware and a record mapping table, and a processor. The processor, when executing the storage firmware, is configured to receive a record identifier, receive a command including data to be stored in the memory, and create an entry in the record mapping table associating the record identifier with a logical block address of the command. The command is received after the record identifier. The processor may receive a playback identifier that includes the record identifier and determine, using the record mapping table, a location of the associated command in the memory. The command is provided to an external device.

Abstract: A data storage device comprising a non-volatile storage medium configured to store data, a data port configured to receive and transmit data between a host computer system and the data storage device and a controller. The controller is configured to receive, via the data port, a first command data structure comprising a status reporting activation and receive, via the data port, a second command data structure. In response to receiving the second command data structure, the controller is configured to, determine a response information associated with the second command data structure, and in response to the status reporting activation, determine a status information, and transmit, via the data port, a response data structure comprising the response information and the status information.

Abstract: Adding a bypass module and a pattern detector module to a data path of a controller will increase the efficiency of both sanitize block erase audit and sanitize crypto erase audit operations. The sanitize crypto erase audit skips an end to end (E2E) protection module to provide decrypted data to a static random access memory (SRAM) buffer and ultimately a host device through a direct memory access (DMA) module. The sanitize block erase audit utilizes the pattern detector module to provide a known pattern to the SRAM buffer and host through the DMA module. The bypass module and pattern detector module feed into a multiplexer (Mux) prior to the SRAM buffer.

Abstract: A controller maintains logical block address (LBA) to physical block address (PBA) mappings as mSets in a storage address table (SAT). Because the SAT may include many mappings, and, consequently, have a large size, the SAT may be stored in a distanced memory from the controller, such as a non-volatile memory device of the data storage device or a host memory buffer of a host device that is coupled to the data storage device. In order to optimize performance, a portion of the SAT may be stored as a compressed address table (CAT) in an internal memory of the controller or another volatile memory of the data storage device. During operation, the controller maintains an active range of mSets in the CAT by adding mSets to the CAT based on whether the LBA is sequential to the active range and a hit count of the active range.

Abstract: The present disclosure generally relates to split, non-operational power states for a data storage device. The data storage device can transition between the split, non-operational power states without advertising the transition to the host device. The power state parameters that are advertised to the host device are adjusted such that the host device is guided to the correct power decision based on the advertised power and duration. By splitting the non-operational power states, the data storage device does not incur additional transitional energy costs for short idle durations.

Abstract: A data storage device comprising a non-volatile storage medium configured to store user data, a data port configured to transmit data between a host computer system and the data storage device, a display system, and a controller. The controller is configured to receive and execute one or more commands from the host computer system to cause a data transfer between the host computer system and the storage medium of the data storage device. The controller generates performance data representing the performance of the data storage device, wherein the performance data includes an efficiency ratio value representing a relative utilization of an operational capability of the data storage device in conducting the data transfer. The controller generates one or more control signals to cause the display system to visually indicate at least the efficiency ratio value of the performance data.

Abstract: A bonded assembly includes a first three-dimensional memory die containing a first alternating stack of first insulating layers and first electrically conductive layers and first memory structures located in the first alternating stack, a second three-dimensional memory die bonded to the first three-dimensional memory die, and containing a second alternating stack of second insulating layers and second electrically conductive layers, and second memory structures located in the second alternating stack. The first electrically conductive layers have different lateral extents along the first horizontal direction that decrease with a respective vertical distance from driver circuit devices, and the second electrically conductive layers have different lateral extents along the first horizontal direction that increase with the respective vertical distance from the driver circuit devices.