Abstract: A data storage device comprising a non-volatile storage medium configured to store user data, a data port configured to transmit data between a host computer system and the data storage device, a display system, and a controller. The controller is configured to receive and execute one or more commands from the host computer system to cause a data transfer between the host computer system and the storage medium of the data storage device. The controller generates performance data representing the performance of the data storage device, wherein the performance data includes an efficiency ratio value representing a relative utilization of an operational capability of the data storage device in conducting the data transfer. The controller generates one or more control signals to cause the display system to visually indicate at least the efficiency ratio value of the performance data.

Abstract: A data storage device and method for accident-mode storage of vehicle information are disclosed. In one embodiment, a data storage device is provided comprising a memory and one or more processors. The memory comprises single-level cell (SLC) memory and multi-level cell (MLC) memory. The one or more processors, individually or in combination, are configured to: receive a command from a vehicle to enter accident mode; and in response to receiving the command from the vehicle to enter accident mode, relocate vehicle information stored in the MLC memory to the SLC memory. Other embodiments are disclosed.

Abstract: Devices and techniques are disclosed wherein an end user can remotely trigger direct data management activities of a data storage device (DSD), such as creating a data snapshot, resetting a snapshot, and setting permissions at the DSD via a remote mobile device app interface.

Abstract: A source-level semiconductor layer and an alternating stack of first material layers and second material layers is formed above a substrate. A hard mask layer is formed over the alternating stack, and is subsequently patterned to provide a pattern of cavities therethrough. Via openings are formed through the alternating stack by performing an anisotropic etch process. A cladding liner is formed on sidewalls of the cavities in the hard mask layer and on a top surface of the hard mask layer. The via openings are vertically extended at least through the source-level semiconductor layer by performing a second anisotropic etch process employing a combination of the cladding liner and the hard mask layer as an etch mask.

Abstract: An integrated circuit (IC) device container/carrier includes a cartridge having a plurality of faces and a device housing slot recessed from one or more of the faces, where each slot is configured to house at least one IC device. The container further includes a lid rotatably coupled with the cartridge, the lid having a window recess configured to align with each device housing slot for accessing corresponding IC devices. At least one of the cartridge faces may be configured as a lock face without a corresponding device housing slot recessed from this lock face.

Abstract: A three-dimensional memory device containing a plurality of levels of memory elements includes a memory film containing a layer stack that includes a resonant tunneling barrier stack, a semiconductor barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the semiconductor barrier layer, a semiconductor channel, and a control gate electrode.

Abstract: The memory device includes a chip with circuitry, a plurality of memory blocks, and a plurality of bit lines. The memory blocks include an array of memory cells, and the circuitry either overlies or underlies the array of memory cells. The bit lines are divided into two portions that are electrically connected with one another via at least one transistor so that at least one portion of each bit line can be charged independently of the other portion of the same bit line.

Abstract: The memory device includes a plurality of memory blocks, each including a plurality of memory cells arranged in a plurality of word lines. Control circuitry is in communication with the plurality of memory blocks. In operation, the control circuitry receives a data write instruction and programs the memory cells of the memory blocks to a one bit per memory cell (SLC) format. In response to the data programmed to the memory cells of the memory blocks in the SLC format reaching an SLC limit prior to completion of the data write instruction, without erasing the memory cells programmed to the SLC format, the control circuitry programs the memory cells of at least some of the plurality of memory blocks from the SLC format to a two bits per memory cell (MLC) format.

Abstract: In some situations, a leak on a wordline may be a localized problem that causes data loss in a block that contains the wordline. In other situations, such as when the leak occurs near a peripheral wordline routing area, the leak can affect the entire memory die. The storage system provided herein has a fatal wordline leak detector that determines the type of leak and, accordingly, whether just the block should be retired or whether related blocks should be retired.

Abstract: A method includes forming an alternating stack of first and second layers, forming a composite hard mask layer over the alternating stack, forming openings in the hard mask, and forming via openings through the alternating stack by performing an anisotropic etch process that transfers a pattern of the openings in the composite hard mask layer through the alternating stack. The compositing hard mask includes a first cladding material layer which has higher etch resistance than upper and lower patterning films of the composite hard mask.

Abstract: A data storage device comprising a non-volatile storage medium configured to store user data, a data port configured to receive and transmit data between a host computer system and the data storage device, and a controller. The controller is configured to receive, via the data port, a write command comprising a read restriction indication, receive, via the data port, data and write the data to an address of the non-volatile storage medium. The controller is further configured to determine an occurrence of a read restriction event, and in response to the occurrence of the read restriction event and in response to the read restriction indication, erase the data from the address of the non-volatile storage medium.

Abstract: A data storage device and method for host-assisted efficient handling of multiple versions of data are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to receive, from a host, identification of different versions of data that are to deleted together, store the different versions of the data in areas of the memory that are erasable in parallel; receive, from the host, a command to erase the different versions of the data; and erase the different versions of the data in parallel. Other embodiments are provided.

Abstract: A data storage device has a controller, a decryption engine, and a memory storing encrypted data. Instead of using the decryption engine to generate a tweak value needed to decrypt the encrypted data, the tweak value is generated by the controller while the controller is waiting for the encrypted data to be read from the memory. This hides the latency to compute the tweak value in the latency to read the encrypted data from the memory.

Abstract: A method for securing a data storage device (DSD) against rogue behaviour by a host, the method executed by a controller of the DSD and comprising: determining a host type of the host; detecting one or more access activities performed by the host on the DSD; processing the one or more access activities to determine a security threat level of the host, wherein the security threat level is determined by weighting one or more corresponding access activity parameters by one or more impact weights; and in response to determining that the security threat level of the host is greater than or equal to a rogue host threat level, controlling the access activities performable by the host on the DSD to safeguard the DSD against the host, wherein the one or more impact weights are dynamically determined based on the host type.

Abstract: Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a read command to read data from the memory device or a write command to write data to the memory device from a host device, determine whether a bottleneck exists in a data/control path between the host device and the memory device, wherein the bottleneck exists in a hardware module of the plurality of hardware modules, and execute a bottleneck release operation when the bottleneck exists in the data/control path between the host device and the memory device, wherein the bottleneck release operation is dependent on whether the bottleneck exists in the input queue. The bottleneck release operation includes changing a clock of the hardware module, moving the command to a different hardware module configured to process the command, and combinations thereof.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to operate under at least a first device protocol and a second device protocol, where the first and second device protocols have different endurance and protection requirements. When data is programmed to the memory device using the first device protocol, but is read from the memory device using the second device protocol, the differing endurance and protection requirements may cause issues in reading the data. In order to alleviate the issues, during idle time of the second device protocol, the controller may program the data using the endurance and protection requirements of the second device protocol to a different portion of the memory device so that the data may be read using either or both device protocols with the appropriate recovery information.

Abstract: A data storage device includes a plurality of hold-up capacitors configured to provide back-up power for a non-volatile memory, a controller, and a write cache. The controller is configured to detect one or more failed hold-up capacitors of the plurality of hold-up capacitors; and in response to detecting the one or more failed hold-up capacitors: perform one or more quiesce operations and determine a count of the one or more failed hold-up capacitors. Based on the count of the one or more failed hold-up capacitors, the controller is configured to reallocate the write buffers of the write cache for use in one or more subsequent write operations.

Abstract: Systems and methods for bit line modulation to compensate for cell source variation are disclosed. For example, a method for reading data from non-volatile storage comprising determining a first bit line level based on a first programmed data state that is being sensed and determining a second bit line level based on a second programmed data state that is being sensed. As another example, a storage device comprising a first bit line driver configured to generate a first bit line level for a first set of bit lines corresponding to a first set of memory strings based on a first cell source level associated with the first set of memory strings a second bit line driver configured to generate a second bit line level for a second set of bit lines corresponding to a second set of memory strings based on a second cell source level associated with the second set of memory strings.