Patents Assigned to SEMI
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Patent number: 12336263Abstract: Techniques for reducing the specific contact resistance of metal-semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal-group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.Type: GrantFiled: September 26, 2023Date of Patent: June 17, 2025Assignee: Acorn Semi, LLCInventors: Walter A. Harrison, Paul A. Clifton, Andreas Goebel, R. Stockton Gaines
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Patent number: 12300324Abstract: A Super Short Channel NOR-type (SSC NOR) flash array is disclosed. Upon the new Channel Induced Ternary Electron programming scheme for resolving the punch-through issue caused by the gate short channel of NVM cell devices, the gate length of NVM cell devices can be further shrunk below 100 nm for NOR flash array. The cell device of SSC NOR flash can be then scaled down to achieve the minimum cell sizes between 4F2 to 5F2, where F is the minimum feature size of a process technology node below 100 nm. In comparison with conventional NOR flash, the SSC NOR flash improves memory density resulting in cost reduction per bit storage. While on the benefit of increasing memory density and storage cost reduction, the invention preserves the typical NOR-type flash advantages over NAND flash on fast nanosecond-range access time, low operating voltages, and high reliability.Type: GrantFiled: February 14, 2023Date of Patent: May 13, 2025Assignee: FS-SEMI SEMICONDUCTOR CORPORATION, LTD.Inventor: Lee Wang
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Publication number: 20250150198Abstract: There are provided a channel coding method, a processing device, a communication method and a device. The channel coding method includes: using a generating matrix or a check matrix of QC-LDPC codes to channel-encode or channel-decode a code stream, wherein a code rate of the generating matrix or the check matrix is 1/4 or 1/3. The method can be used in a transmission environment with a low signal-noise ratio and a long distance.Type: ApplicationFiled: January 14, 2025Publication date: May 8, 2025Applicants: BEIJING ESWIN COMPUTING TECHNOLOGY CO., LTD., Guangzhou Transa Semi Information Technology Co., Ltd.Inventors: Yanqi WU, Yanzhong DAI, Sujiang RONG
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Patent number: 12294376Abstract: Systems and methods are disclosed for differential clock duty cycle correction. For example, a method includes converting an input rail-to-rail differential clock signal to a low-swing differential signal; fixing a DC bias level of the low-swing differential signal; changing DC bias levels of ends of the low-swing differential signal in a complementary manner to change cross-over points of the low-swing differential signal; and inputting the low-swing differential signal to a level shifter and buffer to generate a duty-corrected rail-to-rail digital differential clock signal. For example, an apparatus may include a differential pair of CMOS transmission-gate switches as clock input switches; complementary differential pairs of transistors with gate terminals connected to a differential control voltage signal; and/or extra current sources for independently controlling the DC bias voltages of ends of a differential clock signal.Type: GrantFiled: December 29, 2022Date of Patent: May 6, 2025Assignee: Alphawave Semi, Inc.Inventors: Santosh Mahadeo Narawade, Jithin K, Ayan Dutta
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Patent number: 12287364Abstract: A test system includes a to-be-tested die including a to-be-tested transistor and a sense transistor, and a test device including a signal amplifying unit, a testing unit, and a probe card connecting the signal amplifying unit and the testing unit to the die. The signal amplifying unit has a first terminal connected to the to-be-tested transistor, and second and third terminals connected to the sense transistor. The signal amplifying unit stabilizes voltages at the second and third terminals based on a voltage at the first terminal, and generates an amplification voltage based on the voltages at the first to third terminals. The testing unit provides test signals to the to-be-tested transistor, determines magnitudes of currents flowing through the to-be-tested transistor and the sense transistor based on the test signals, the amplification voltage and a predetermined resistance, and thus acquires a current ratio to determine whether the die is defective.Type: GrantFiled: June 29, 2023Date of Patent: April 29, 2025Assignee: LEADPOWER-SEMI CO., LTD.Inventors: Cheng-Jyun Wang, Po-Hsien Li, Jen-Hao Yeh
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Patent number: 12267159Abstract: There are provided a channel coding method, a processing device, a communication method and a device. The channel coding method includes: using a generating matrix or a check matrix of QC-LDPC codes to channel-encode or channel-decode a code stream, wherein a code rate of the generating matrix or the check matrix is 1/6, 1/4 or 1/3. The method can be used in a transmission environment with a low signal-noise ratio and a long distance.Type: GrantFiled: February 17, 2023Date of Patent: April 1, 2025Assignees: Beijing ESWIN Computing Technology Co., Ltd., Guangzhou Transa Semi Information Technology Co., Ltd.Inventors: Yanqi Wu, Yanzhong Dai, Sujiang Rong
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Patent number: 12265181Abstract: A scanner and coaxial and non-coaxial lidar systems with the scanner are provided. The scanner includes a wafer substrate, optical switches, and grating antenna groups; optical switches and the grating antenna groups are fixed on an upper end of the wafer substrate, one grating antenna group is optically connected to one optical switch port; the grating antenna groups are distributed in an array to form a grating part, and an upper side of the grating part is covered with a lens module. Two-dimensional scanning is performed by the scanner, combined with distance information in the third dimension calculated by the system, achieving three-dimensional imaging. Through joint participation of an optical amplifier and grating antenna groups, noise removal is realized, reducing external interference on detection results. The system is integrated on a chip, has a small size and is easy to install, which is convenient for cost reduction and mass production.Type: GrantFiled: September 3, 2021Date of Patent: April 1, 2025Assignee: Hangzhou Xight Semi-conductor Co., Ltd.Inventors: Jinxi Huang, Zihao Shan
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Patent number: 12230519Abstract: An apparatus for a direct transfer of a semiconductor device die from a wafer tape to a substrate. A first frame holds the wafer tape and a second frame secures the substrate. The second frame holds the substrate such that a transfer surface is disposed facing the semiconductor device die on a first side of the wafer tape. A needle is disposed adjacent a second side of the wafer tape opposite the first side. A length of the needle extends in a direction toward the wafer tape. A first needle actuator is used to adjust an angle of the needle to align the die, wafer tape, and transfer surface at which point the needle presses on the second side of the wafer tape to press a semiconductor device die of the one or more semiconductor device die into contact with the transfer surface of the substrate.Type: GrantFiled: May 23, 2022Date of Patent: February 18, 2025Assignee: COWLES SEMI, LLCInventors: Sean Kupcow, Nicholas Steven Busch, Justin Wendt
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Patent number: 12218692Abstract: A method of constructing a base matrix of a permutation matrix, device and medium. The method includes: determining a number Ns of columns corresponding to systematic bits and a number Nrow of rows of the base matrix according to a code rate of the permutation matrix; determining a maximum row weight dc and a total weight range Tweight of the base matrix, wherein the row weight is dc or dc?1; according to Tweight and Nrow, determining a first range R1 of rows with weights of dc?1 and a second range R2 of rows with weights of dc in the base matrix; according to Nrow, Tweight, R1 and R2, filling the systematic bit part in an initial base matrix corresponding to the base matrix to obtain an intermediate base matrix; and performing convergence calculation on it to determine whether it converges, and determining it as the base matrix if it converges.Type: GrantFiled: February 15, 2023Date of Patent: February 4, 2025Assignees: Beijing ESWIN Computing Technology Co., Ltd., Guangzhou Transa Semi Information Technology Co., Ltd.Inventors: Yanqi Wu, Yanzhong Dai, Sujiang Rong
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Patent number: 12202129Abstract: Disclosed are a pick tip apparatus method interchanging pick tip assemblies within the same. The pick tip apparatus includes a housing having a housing channel. The apparatus further includes a fitting connected to the housing channel. The fitting is configured to accept an external vacuum source for applying a vacuum to the housing channel. The apparatus further includes a magnet and a pick tip assembly. The pick tip assembly is releasably held within the housing channel magnetically by the magnet. The pick tip assembly includes a vacuum cup and a pick tip body. The pick tip body has a pick tip body channel in communication with the housing channel and configured to apply the vacuum from the housing channel to the vacuum cup.Type: GrantFiled: October 27, 2023Date of Patent: January 21, 2025Assignee: Boston Semi Equipment LLCInventors: Larry Stuckey, John Murach, John Lewis, Kent Blumenshine, Jason Chalfant, Colin Scholefield
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Patent number: 12199046Abstract: A die can be applied to a front conductive layer. Openings can be formed in the conductive layer over contact points on the die. The openings can be filled with a conductive material to electrically couple the conductive layer to the contact points on the die. The front conductive layer can be etched to form a first conductive pattern. Conductive standoffs can be formed on portions of the front conductive layer. An additional front conductive layer can be laminated onto the front side. Openings can be formed in the additional front conductive layer over the standoffs. The openings can be filled with a conductive material to electrically couple the additional conductive layer to the underlying standoffs. The additional conductive layer can be etched to form a second conductive pattern.Type: GrantFiled: March 16, 2023Date of Patent: January 14, 2025Assignee: FARADAY SEMI, INC.Inventors: Martin Standing, Parviz Parto
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Patent number: 12165895Abstract: An apparatus for executing a direct transfer of a semiconductor device die from a first substrate to a second substrate. The apparatus includes a first substrate conveyance mechanism movable in two axes. A micro-adjustment mechanism is coupled with the first substrate conveyance mechanism and is configured to hold the first substrate and to make positional adjustments on a scale smaller than positional adjustments caused by the first substrate conveyance mechanism. The micro-adjustment mechanism includes a micro-adjustment actuator having a distal end and a first substrate holder frame that is movable via contact with the distal end of the micro-adjustment actuator. A second frame is configured to secure the second substrate such that a transfer surface is disposed facing the semiconductor device die disposed on a surface of the first substrate. A transfer mechanism is configured to press the semiconductor device die into contact with the transfer surface of the substrate.Type: GrantFiled: August 14, 2023Date of Patent: December 10, 2024Assignee: Cowles Semi, LLCInventors: Andrew Huska, Justin Wendt, Luke Dupin, Cody Peterson
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Publication number: 20240405722Abstract: The disclosure provides a common mode voltage dynamic modulation circuit, a method thereof and a class-D audio power amplifier. The modulation circuit includes: a signal input terminal and a common mode voltage dynamic adjustment module. The signal input terminal is used to receive an audio signal and output a differential audio signal to the common mode voltage dynamic adjustment module. The common mode voltage dynamic adjustment module is used to dynamically adjust a common mode voltage of the differential audio signal according to a preset static common mode bias and a normalized processing result of a swing of the audio signal, track an amplitude of an input audio signal in real time and obtain a continuously adjusted common mode voltage.Type: ApplicationFiled: December 27, 2022Publication date: December 5, 2024Applicant: Suzhou ACME Semi Co.Ltd.Inventor: Shuangxi DING
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Patent number: 12160252Abstract: There are provided a method for constructing a permutation matrix or a check matrix, a processing device, a storage medium and a coding method. The method of constructing a permutation matrix includes: obtaining a base matrix used for the permutation matrix; and lifting the base matrix to obtain the permutation matrix, which includes: obtaining a protograph of the base matrix; and obtaining each macro-cycle in the protograph, and for each macro-cycle in the protograph, determining a size of a short cycle corresponding to the macro-cycle in a Tanner graph of the check matrix corresponding to the permutation matrix by an equivalent cyclic value ECS of the macro-cycle, and determining whether at least one cyclic value in the macro-cycle needs to be set according to the size of the short cycle.Type: GrantFiled: February 14, 2023Date of Patent: December 3, 2024Assignees: Beijing ESWIN Computing Technology Co., Ltd., Guangzhou Transa Semi Information Technology Co., Ltd.Inventors: Yanqi Wu, Yanzhong Dai, Sujiang Rong
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Publication number: 20240369863Abstract: Provided are a micro-ring resonator and an electronic device. The micro-ring resonator includes a multi-mode straight waveguide and a micro-ring waveguide, and the micro-ring waveguide and the multi-mode straight waveguide are in a coupling relationship with each other; the multi-mode straight waveguide and the micro-ring waveguide have a coupling region; a portion of the multi-mode straight waveguide disposed in the coupling region is configured to transmit at least two optical signals so that the transmission spectrum of the micro-ring resonator is a Fano resonance line-shape transmission spectrum.Type: ApplicationFiled: August 1, 2022Publication date: November 7, 2024Applicant: SUZHOU DAWNING SEMI TECHNOLOGY CO., LTD.Inventor: Yao WANG
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Patent number: 12136676Abstract: Schottky diode and method for fabricating the same disclosed. The Schottky diode includes a gallium oxide layer that is a semiconductor layer doped with a first-type dopant, a cathode in ohmic contact with the gallium oxide layer and an anode having a Schottky contact metal layer in Schottky contact with the gallium oxide layer. The gallium oxide layer is in contact with an interface with the Schottky contact metal layer, contains a second-type dopant of a conductivity opposite to that of the first-type dopant, and has an interlayer which is a region where a concentration of the second-type dopant decreases as it moves away from an interface with the Schottky contact metal layer.Type: GrantFiled: March 24, 2020Date of Patent: November 5, 2024Assignee: POWERCUBE SEMI INC.Inventors: You Seung Rim, Tai Young Kang, Sin Su Kyoung
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Publication number: 20240349763Abstract: Provided are millet and food products made from millet having reduced lipase activity. Also provided are nucleic acid sequences, constructs, expression cadettes, markers, primers probes, methods, gene editing tools, and materials useful in producing millet with reduced lipase activity as well as millet food products with reduced rancidity.Type: ApplicationFiled: August 10, 2022Publication date: October 24, 2024Applicants: PIONEER HI-BRED INTERNATIONAL, INC., INTERNATIONAL CROPS RESEARCH INSTITUTE FOR THE SEMI-ARID TROPICSInventors: RASIKA RAJENDRA AHER, POOJA BHATNAGAR-MATHUR, JOHN D. EVERARD, KAYLA S. FLYCKT, WILLIAM JAMES GORDON-KAMM, SUDHAKAR REDDY PALAKOLANU, KIRAN K. SHARMA, LAURA L. WAYNE
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Patent number: 12118175Abstract: Existing content such as books are reorganized and condensed as electronic books for display on a mobile computing device. The electronic books have a hierarchical structure. A user interacts with the content of the book by way of a touch screen of the mobile computing device. The navigation may be non-linear in nature and the book is reconstructed as a set of primary ideas, supporting ideas, stacks of cards for the supporting ideas, and individual cards comprising elements and commentary from or about the book.Type: GrantFiled: April 19, 2021Date of Patent: October 15, 2024Assignee: Semi-Linear, Inc.Inventor: Linda M. Holliday
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Patent number: 12119823Abstract: Systems and methods are disclosed for wide frequency range voltage controlled oscillators. For example, an apparatus includes a Voltage Controlled Oscillator (VCO) including a delay cell which includes first and second current sources provided in parallel with one another. The first current source is controlled by a voltage control input connected to a voltage control terminal and the second current source is controlled by a bias voltage input connected to a bias voltage terminal. The first current source provides an alternate current path in the delay cell when the second current source is off. The delay cell is operable to receive an input and produce an output using the alternate current path.Type: GrantFiled: November 29, 2022Date of Patent: October 15, 2024Assignee: Alphawave Semi, Inc.Inventors: Santosh Mahadeo Narawade, Jithin K, Mohit Gupta
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Patent number: D1047556Type: GrantFiled: August 13, 2021Date of Patent: October 22, 2024Assignee: SEMI EXACT, INC.Inventor: Benjamin Uyeda