Abstract: Systems and methods of charge-neutralizing charged particle beams are contemplated, wherein an originating beam is transited through a sequence of slow wave recombination chambers and exposed to neutralizing beams while transit therethrough in order to produce a neutral particle beam. These systems and methods may be seen to be especially suitable for use in spacecraft or other ungrounded environments where the removal of excess charge buildup represents a substantial barrier, and when utilized in a directed energy weapon, may greatly increase the rate at which successive beam pulses may be directed against a target or against multiple targets.

Abstract: A power converter can include first, second, third, and fourth switches, and a driver for operating the drive switches to modify an input voltage and provide an output voltage. An AC coupling capacitor can be coupled between the first and fourth switches. The first, second, third, and fourth switches can control current through two inductors. The power converter can have a fifth switch, which can provide a discharge path for discharging the first inductor, the second inductor, and/or the capacitor. Another capacitor can be between the fifth switch and ground. The power converter can provide an output voltage that is at least about ? of the input voltage. The power converter can include resonance circuitry, such as a third inductor, for soft switching the fifth switch.

Abstract: A resonant charge pump circuit includes a resonant circuit having a bucket capacitor and a bucket inductor connected in series, and a switching circuit connected to the resonant circuit. The switching circuit switches to a first state that enables current to flow from an input terminal into the resonant circuit to charge the bucket capacitor and the bucket inductor, and switches to a second state that enables current to flow from the resonant circuit to discharge the bucket capacitor and the bucket inductor to an output terminal. The resonant circuit controls current flow into and out from the resonant circuit when the switching circuit switches between the states. The resonant charge pump circuit also includes a timing circuit that controls when the switching circuit switches between the states.

Abstract: An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.

Abstract: A method for preparing a super junction trench MOSFET, comprising: providing a substrate, and forming a first trench in the substrate; depositing an epitaxial portion of a first stage in the first trench while supplying a doped gas and an etching gas, and performing an epitaxial process after stopping supplying the doped gas and the etching gas, wherein impurities in the epitaxial portion of the first stage are diffused to an upper portion of the first trench and to form an epitaxial portion of a second stage with a gradient concentration by utilizing a high-temperature environment of the epitaxial process; forming a well region, a trench gate, and an active region in the substrate at a periphery of the first trench; forming an interlayer dielectric layer covering the column, the trench gate, and the active region; and electrically leading out the column, the trench gate, and the active region.

Abstract: Provided is a probe card, comprising a guide plate and a shielding structure of single-layer or multi-layer. The guide plate comprises an upper surface, a lower surface, and at least one guide hole passing through the upper surface and the lower surface, and the guide hole is provided with an inner wall surface. At least one layer of the shielding structure is made of an electromagnetic absorption material or an electromagnetic reflection material, and the shielding structure is not connected to a ground. Each layer of the shielding structure is formed on the inner wall surface of the guide hole by means of atomic layer deposition or atomic layer etching, and a thickness of each layer is less than 1000 nm.

Abstract: Embodiments of the present application provide a GRPC-based chip test method, a GRPC-based chip test apparatus, and a storage medium. The GRPC-based chip test method comprises: determining a number of to-be-tested chips that actually need to be tested among to-be-tested chips, and issuing a corresponding number of remote instrument call requests according to the number of to-be-tested chips that actually need to be tested; acquiring each of the remote instrument call requests based on a GRPC protocol; and sorting all the remote instrument call requests to form a request execution sequence table, and controlling the test instrument to sequentially test the to-be-tested chips that actually need to be tested according to the request execution sequence table.

Abstract: A means of making a multi ply structural panel by eliminating the top liner in the corrugating process. The present invention is made possible through modification to the corrugating rolls of the singlefacer. The design modification to the rolls involves incorporation of slots that run around the circumference of one roll and mating creasing tools incorporated around the circumference of the other of the corrugated roll set. These slots and creasing tools are incorporated across the existing flutes of the corrugating rolls.

Abstract: A system is provided that predicts motor wear and failures before they occur. Telemetry data from motors in a motor application is collected and predictive algorithms are used to determine when a motor is aging and when it may fail. Identifying a potential failure in these types of applications can help mitigate risk of other equipment failures and realize cost savings. In one example, a motor aging detection system is provided that includes one or more DC motors, and a motor controller coupled to each motor. The motor controller reads three phase currents from each motor and converts the phase currents to digital values, calculates telemetry data including applied voltages, back electric-motive force, inductance, and resistance of each motor at periodic intervals, stores this telemetry data for each motor in a memory. An age detection circuit retrieves this information from the memory and determines age factors of the motor.

Abstract: A power converter can include first, second, third, and fourth power switches, and a driver for operating the drive switches to modify an input voltage. An AC coupling capacitor can be coupled between the first and fourth power switches. Bootstrap capacitors can be used for driving the first and second power switches, which can be high-side switches. In some embodiments, a current sensing circuit can be used to measure current through the third and/or fourth power switches and for determining the current through the power converter. In some embodiments, the power converter can monitor the voltage across the AC coupling capacitor and can determine the current through the power converter based on the monitored voltages. In some embodiments, the AC coupling capacitor can be pre-charged before the power converter begins normal operation.

Abstract: An electrical contact structure (an MIS contact) includes one or more conductors (M-Layer), a semiconductor (S-Layer), and an interfacial dielectric layer (I-Layer) of less than 4 nm thickness disposed between and in contact with both the M-Layer and the S-Layer. The I-Layer is an oxide of a metal or a semiconductor. The conductor of the M-Layer that is adjacent to and in direct contact with the I-Layer is a metal oxide that is electrically conductive, chemically stable and unreactive at its interface with the I-Layer at temperatures up to 450° C. The electrical contact structure has a specific contact resistivity of less than or equal to approximately 10?5-10?7 ?-cm2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 2×1019 cm?3 and less than approximately 10?8 ?-cm2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 1020 cm?3.

Abstract: Disclosed are a pick tip apparatus method interchanging pick tip assemblies within the same. The pick tip apparatus includes a housing having a housing channel. The apparatus further includes a fitting connected to the housing channel. The fitting is configured to accept an external vacuum source for applying a vacuum to the housing channel. The apparatus further includes a magnet and a pick tip assembly. The pick tip assembly is releasably held within the housing channel magnetically by the magnet. The pick tip assembly includes a vacuum cup and a pick tip body. The pick tip body has a pick tip body channel in communication with the housing channel and configured to apply the vacuum from the housing channel to the vacuum cup.

Abstract: Techniques for reducing the specific contact resistance of metal-semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal-group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.

Abstract: A means of making a multi ply structural panel by eliminating the top liner in the corrugating process. The present invention is made possible through modification to the corrugating rolls of the singlefacer. The design modification to the rolls involves incorporation of slots that run around the circumference of one roll and mating creasing tools incorporated around the circumference of the other of the corrugated roll set. These slots and creasing tools are incorporated across the existing flutes of the corrugating rolls.

Abstract: A semiconductor structure includes a layer arrangement consisting of, in sequence, a semiconductor-on-insulator layer (SOI) over a buried oxide (BOX) layer over a buried stressor (BS) layer with a silicon bonding layer (BL) intervening between the BOX and the BS layers. The semiconductor structure may be created by forming the BS layer on a substrate of a first wafer; growing the BL layer at the surface of the BS layer; wafer bonding the first wafer to a second wafer having a silicon oxide layer formed on a silicon substrate such that the silicon oxide layer of the second wafer is bonded to the BL layer of the first wafer, and thereafter removing a portion of the silicon substrate of the second wafer.

Abstract: A scanner and coaxial and non-coaxial lidar systems with the scanner are provided. The scanner includes a wafer substrate, optical switches, and grating antenna groups; optical switches and the grating antenna groups are fixed on an upper end of the wafer substrate, one grating antenna group is optically connected to one optical switch port; the grating antenna groups are distributed in an array to form a grating part, and an upper side of the grating part is covered with a lens module. Two-dimensional scanning is performed by the scanner, combined with distance information in the third dimension calculated by the system, achieving three-dimensional imaging. Through joint participation of an optical amplifier and grating antenna groups, noise removal is realized, reducing external interference on detection results. The system is integrated on a chip, has a small size and is easy to install, which is convenient for cost reduction and mass production.

Abstract: During nanoscale manufacture on a substrate, payload active agents are loaded on a delivery platform, with a release layer between the delivery platform and the payload active agent and an encapsulate over the payload active agent. The combined delivery platform, release layer, active agent payload, and encapsulant form a nanoscale drug delivery vehicle for subsequent delivery to a patient. The nanoscale drug delivery vehicle is small enough to permeate through the cell and deliver the payload active agent within the cell via reducing the retaining functionality of the release layer and degrading of the encapsulant. The nanoscale drug delivery vehicle offers a series of improved features including greater control of size, shape, dosage, bioavailability, cell targeting, and release timing.

Abstract: A hardware accelerator that is efficient at performing computations related to a neural network. In one embodiment, the hardware accelerator includes a first data buffer that receives input data of a layer in the neural network and shift the input data slice by slice downstream. The hardware accelerator includes a second data buffer that receives kernel data of the layer in the neural network and shift the kernel data slice by slice downstream. The hardware accelerator includes a first input shift register that receives an input data slice from the first data buffer. The first input shift register may correspond to a two-dimensional shift register configured to shift values in the input data slice in x and y directions. The hardware accelerator includes a second input shift register that receives a kernel data slice from the second data buffer. A multiplication block performs convolution of the input and kernel data.

Abstract: A charged particle buncher includes a series of spaced apart electrodes arranged to generate a shaped electric field. The series includes a first electrode, a last electrode and one or more intermediate electrodes. The charged particle buncher includes a waveform device attached to the electrodes and configured to apply a periodic potential waveform to each electrode independently in a manner so as to form a quasi-electrostatic time varying potential gradient between adjacent electrodes and to cause spatial distribution of charged particles that form a plurality of nodes and antinodes. The nodes have a charged particle density and the antinodes have substantially no charged particle density, and the nodes and the antinodes are formed from a charged particle beam configured to hit the target.

Abstract: The present disclosure relates to an LED lighting device for strawberry seedling raising. The LED lighting device for strawberry seedling raising according to an exemplary embodiment of the present disclosure includes: a light emitting unit composed of a first light emitting part composed of a red region wavelength emission LED and a blue region wavelength emission LED and a second light emitting part composed of the red region wavelength emission LED and an infrared region wavelength emission LED; and a control part for controlling the light emitting unit to manage a strawberry seedling raising, and controlling each LED included in the first light emitting part or the second light emitting part to be turned on/off based on a preset seedling raising mode.