Abstract: Existing content such as books are reorganized and condensed as electronic books for display on a mobile computing device. The electronic books have a hierarchical structure. A user interacts with the content of the book by way of a touch screen of the mobile computing device. The navigation may be non-linear in nature and the book is reconstructed as a set of primary ideas, supporting ideas, stacks of cards for the supporting ideas, and individual cards comprising elements and commentary from or about the book.

Abstract: Tensile strained germanium is provided that can be sufficiently strained to provide a nearly direct band gap material or a direct band gap material. Compressively stressed or tensile stressed stressor materials in contact with germanium regions induce uniaxial or biaxial tensile strain in the germanium regions. Stressor materials may include silicon nitride or silicon germanium. The resulting strained germanium structure can be used to emit or detect photons including, for example, generating photons within a resonant cavity to provide a laser.

Abstract: A current sense method comprises generating a voltage across a first current mirror of a current sense apparatus, the voltage being proportional to a current flowing through the current sense apparatus when the current is greater than a predetermined current value and applying a minimum drain-to-source voltage limiter to the first current mirror of the current sense apparatus when the current is less than the predetermined current value, wherein, as a result of applying the minimum drain-to-source voltage limiter to the first current mirror, the voltage across the first current mirror is clamped to a predetermined voltage value.

Abstract: A photodetector-array and fabrication method thereof are disclosed. The photodetector-array includes a first and second semiconductor structures having respective active regions defining respective pluralities of active photodetectors and active readout integrated circuit pixels (RICPs) electronically connectable to one another respectively. The first and second semiconductor structures are made with different semiconductor materials/compositions having different first and second coefficients of thermal expansion (CTEs) respectively. The pitch distances of the active photodetectors and the pitch distances of the respective active RICPs are configured in accordance with the difference between the first and second CTEs, such that at high temperatures, at which electrical coupling between the first and second semiconductor structures is performed, the electric contacts of the active photodetectors and of their respective RICPs overlap.

Abstract: An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.

Abstract: Photodetectors and methods for dual band photo detection are disclosed. The photodetector includes a stack of semiconductor layers defining first and second unipolar photosensitive modules (UPMs) of respectively opposite doping polarities, and a contact layer including at least one of metal and semiconductor materials having doping polarity opposite to that of the second UPM. The first and second UPMs are adapted for sensing radiation of different respective first and second wavelengths ranges. The second UPM is located upon the first UPM thereby forming a first diode junction between the first and second UPMs. The contact layer is located on the second UPM thereby forming a second diode junction between the second UPM and the contact layer. The first and second diode junctions are configured to have respectively opposite conduction directions, enabling selective sensing of electrical signals associated with the first and second wavelengths ranges.

Abstract: A charged particle buncher includes a series of spaced apart electrodes arranged to generate a shaped electric field. The series includes a first electrode, a last electrode and one or more intermediate electrodes. The charged particle buncher includes a waveform device attached to the electrodes and configured to apply a periodic potential waveform to each electrode independently in a manner so as to form a quasi-electrostatic time varying potential gradient between adjacent electrodes and to cause spatial distribution of charged particles that form a plurality of nodes and antinodes. The nodes have a charged particle density and the antinodes have substantially no charged particle density, and the nodes and the antinodes are formed from a charged particle beam with an energy less than or equal to 500 keV.

Abstract: An electrical contact structure (an MIS contact) includes one or more conductors (M-Layer), a semiconductor (S-Layer), and an interfacial dielectric layer (I-Layer) of less than 4 nm thickness disposed between and in contact with both the M-Layer and the S-Layer. The I-Layer is an oxide of a metal or a semiconductor. The conductor of the M-Layer that is adjacent to and in direct contact with the I-Layer is a metal oxide that is electrically conductive, chemically stable and unreactive at its interface with the I-Layer at temperatures up to 450° C. The electrical contact structure has a specific contact resistivity of less than or equal to approximately 10?5-10?7 ?-cm2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 2×1019 cm?3 and less than approximately 10?8 ?-cm2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 1020 cm?3.

Abstract: The present disclosure provides, a DNA construct comprising a polynucleotide fragment comprising a first, and a second sequence, wherein said first sequence encodes a mitochondrial transit peptide, said second sequence encodes a polypeptide having amino acid sequence as set forth in SEQ ID NO: 1, and said polynucleotide fragment is operably linked to a flower specific promoter. The present disclosure also provides with a DNA vector, a recombinant host cell and a method of obtaining the same.

Abstract: A cleaning apparatus of an exhaust path of a process reaction chamber used in a manufacturing of articles including a semiconductor or an LCD. The cleaning apparatus of the exhaust path includes a housing having an inflow pipe, connected to an upstream end of the exhaust path, an outflow pipe, connected to a downstream end of the exhaust path, and a connecting pipe disposed between the inflow pipe and the outflow pipe. A radio frequency generator in the housing applies radio frequency power to the inflow pipe and to the outflow pipe via respective coils. Plasma induced within the inflow and outflow pipes from RF power applied via the respective coils causes the generation of radicals from the exhaust gas flowing within. The radicals act to dislodge accumulated particulates within the exhaust path downstream of the cleaning apparatus.

Abstract: Methods and structures are provided for wafer-level packaging of light-emitting diodes (LEDs). An array of LED die are mounted on a packaging substrate. The substrate may include an array of patterned metal contacts on a front side. The metal contacts may be in electrical communication with control logic formed in the substrate. The LEDs mounted on the packaging substrate may also be encapsulated individually or in groups and then singulated, or the LEDs mounted on the packaging substrate may be integrated with a micro-mirror array or an array of lenses.

Abstract: A nanowire transistor includes undoped source and drain regions electrically coupled with a channel region. A source stack that is electrically isolated from a gate conductor includes an interfacial layer and a source conductor, and is coaxially wrapped completely around the source region, extending along at least a portion of the source region. A Schottky barrier between the source conductor and the source region is a negative Schottky barrier and a concentration of free charge carriers is induced in the semiconductor source region.

Abstract: Techniques for reducing the specific contact resistance of metal—semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal—group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.

Abstract: One or more chip-embedded integrated voltage regulators (“CEIVR's”) are configured to provide power to a circuit or chip such as a CPU or GPU and meet power delivery specifications. The CEIVR's, circuit or chip, and power delivery pathways can be included within the same package. The CEIVR's can be separate from the circuit or chip.

Abstract: A mechanical system, such as cryogenic refrigerator system, is described. The system comprises two or more axial moving elements generating two or more cyclic forces along parallel axes and a vibration attenuation unit. The cyclic forces are provided with common frequency and certain phase difference between them. The vibration attenuation unit is configured for attenuating vibrations corresponding to two or more modes of vibrations characterized by a frequency corresponding to operation frequency of said two or more cyclic forces.

Abstract: A processor includes a pipeline and a multi-bank Branch-Target Buffer (BTB). The pipeline is configured to process program instructions including branch instructions. The multi-bank BTB includes a plurality of BTB banks and is configured to store learned Target Addresses (TAs) of one or more of the branch instructions in the plurality of the BTB banks, to receive from the pipeline simultaneous requests to retrieve respective TAs, and to respond to the requests using the plurality of the BTB banks in the same clock cycle.

Abstract: An apparatus comprises a positive data input/output terminal configured to be connected with a positive data line of a USB device, wherein the positive data input/output port is weakly pulled up to a first voltage potential through a pull-up resistor, a negative data input/output terminal configured to be connected with a negative data line of the USB device, wherein the negative data input/output terminal is connected to a second voltage potential, a window comparator having an input detecting a voltage across the two data input/output terminals and a wake-up signal generator connected to an output of the window comparator, wherein the wake-up signal generator is configured to generate a signal for adjusting a switching frequency of a power converter after the USB device is connected to the power converter.

Abstract: An Inorganic Lift-Off-Profile-Process (referred to herein as “ILOPP”) is described wherein a portion of a surface inorganic oxide is etched from a substrate oxide surface and under a photoresist edge that supports a sacrificial metal layer. This oxide etched profile under the sacrificial photoresist/metal edge improves Lift-Off of the sacrificial metal layer and delivers smoother, improved metal edge definition in addition to an improved planer surface (flatness) as compared to known LOP technologies.

Abstract: A power management integrated circuit includes pairs of high-side and low-side drivers, sensing circuitry, and a processor. The high-side and low-side drivers are used in combination with external discrete NFETs to drive multiple windings of a motor. The N-channel LDMOS transistor of each high-side driver has an associated isolation structure and a tracking and clamping circuit. If the voltage on a terminal of the integrated circuit pulses negative during a switching of current flow to the motor, then the isolation structure and tracking and clamping circuit clamps the voltage on the isolation structure and blocks current flow from the substrate to the drain. An associated ESD protection circuit allows the voltage on the terminal to pulse negative. As a result, a large surge of current that would otherwise flow through the high-side driver is blocked, and is conducted outside the integrated circuit through a body diode of an external NFET.

Abstract: A Dynamic Triggering and Sample Engine (DTSE) that detects a first trigger received on a trigger input terminal that triggers a series of analog-to-digital conversions to be completed by an analog-to-digital converter circuit. The DTSE then determines a first sequence configuration stored in a sequence configuration table that is associated with the first trigger, causes a first analog-to-digital conversion to be performed using the first sequence configuration; causes a first analog-to-digital conversion result value to be stored in a sequence result table; and outputs an interrupt to a processor indicating that the first analog-to-digital conversion result value is available in the sequence result table. The interrupt is output from the DTSE before all remaining analog-to-digital conversions in the series are completed. In response to receiving the interrupt, the processor reads the analog-to-digital result value from the sequence result table via a bus.