Abstract: Systems and methods for monitoring, characterizing and managing communications between and amongst data packet sources are provided, for example by providing Safety Integrity Level of Services (SILoS) for of System-On-Chip (SOC) and/or Network-on-Chip (NOC) deployments. For example, disclosed herein is a controller, that in combination with digital logic circuitry, is configured to receive data packets transmitted between intellectual property blocks of a SOC or NOC deployment for assuring correct sequencing, monitor received signals to detect or predict faults therein, and generate an indication signal indicative of the fault. The indication signal used by a performance analysis system executing software for diagnostic, prognostic analysis.

Abstract: The present disclosure provides, a DNA construct comprising a polynucleotide fragment comprising a first, and a second sequence, wherein said first sequence encodes a mitochondrial transit peptide, said second sequence encodes a polypeptide having amino acid sequence as set forth in SEQ ID NO: 1, and said polynucleotide fragment is operably linked to a flower specific promoter. The present disclosure also provides with a DNA vector, a recombinant host cell and a method of obtaining the same.

Abstract: A power converter can include first, second, third, and fourth power switches, and a driver for operating the drive switches to modify an input voltage. An AC coupling capacitor can be coupled between the first and fourth power switches. Bootstrap capacitors can be used for driving the first and second power switches, which can be high-side switches. In some embodiments, a current sensing circuit can be used to measure current through the third and/or fourth power switches and for determining the current through the power converter. In some embodiments, the power converter can monitor the voltage across the AC coupling capacitor and can determine the current through the power converter based on the monitored voltages. In some embodiments, the AC coupling capacitor can be pre-charged before the power converter begins normal operation.

Abstract: An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

Abstract: A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate structure. The channel and the insulated gate structure define a first and second undercut void regions that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively. A passivation layer is included on at least one exposed sidewall surface of the channel and metal source and drain terminals are located on respective first and second sides of the channel, including on the passivation layer and within the undercut void regions beneath the insulated gate structure. At least one of the metal source and drain terminals comprises a metal that has a work function near a valence band of the p-type substrate.

Abstract: An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

Abstract: A system comprises an integrated circuit package, an inductor that is part of a power supply, and a printed circuit board (PCB) having a metal trace disposed directly below the inductor when viewed from a top-down perspective. The integrated circuit package includes a first terminal, a second terminal, and a novel inductor current detection and calibration circuit. The first terminal is coupled to a first end of the metal trace and the second terminal is coupled to a second end of the metal trace. During operation of the power supply, the novel circuit detects an OCP condition whereby an output current of the power supply exceeds an OCP level. The novel circuit detects the OCP condition in part by sensing a voltage across the metal trace. After calibration at room temperature, the novel circuit performs accurate OCP detection over a range of temperatures without using any temperature sensor near inductor.

Abstract: An integrated circuit (IC) comprises a regulator circuit, a bootstrap control circuit, and a gate driver that drives a transistor pair in buck or boost mode to switch current through an inductor. The IC has a VIN terminal coupled to receive a voltage generated from an AC power source, a STR terminal coupled to receive a voltage from a stored power source (e.g., a capacitor bank), and a HSB terminal that is capacitively coupled to the inductor. When bucking or boosting, the regulator circuit generates VDD supply voltage from the stored power source, supplies the VDD supply voltage onto the bootstrap control circuit, and the bootstrap control circuit generates a gate driver supply voltage that is supplied to the gate driver circuit. When not bucking or boosting, voltage on the HSB terminal is maintained between a voltage threshold from the AC power source without draining the stored power source.

Abstract: A charged particle buncher includes a series of spaced apart electrodes arranged to generate a shaped electric field. The series includes a first electrode, a last electrode and one or more intermediate electrodes. The charged particle buncher includes a waveform device attached to the electrodes and configured to apply a periodic potential waveform to each electrode independently in a manner so as to form a quasi-electrostatic time varying potential gradient between adjacent electrodes and to cause spatial distribution of charged particles that form a plurality of nodes and antinodes. The nodes have a charged particle density and the antinodes have substantially no charged particle density, and the nodes and the antinodes are formed from a charged particle beam with an energy greater than 500 keV.

Abstract: An integrated circuit (IC) comprises a regulator circuit, a bootstrap control circuit, and a gate driver that drives a transistor pair in buck or boost mode to switch current through an inductor. The IC has a VIN terminal coupled to receive a voltage generated from an AC power source, a STR terminal coupled to receive a voltage from a stored power source (e.g., a capacitor bank), and a HSB terminal that is capacitively coupled to the inductor. When bucking or boosting, the regulator circuit generates VDD supply voltage from the stored power source, supplies the VDD supply voltage onto the bootstrap control circuit, and the bootstrap control circuit generates a gate driver supply voltage that is supplied to the gate driver circuit. When not bucking or boosting, voltage on the HSB terminal is maintained between a voltage threshold from the AC power source without draining the stored power source.

Abstract: Existing content such as books are reorganized and condensed as electronic books for display on a mobile computing device. The electronic books have a hierarchical structure. A user interacts with the content of the book by way of a touch screen of the mobile computing device. The navigation may be non-linear in nature and the book is reconstructed as a set of primary ideas, supporting ideas, stacks of cards for the supporting ideas, and individual cards comprising elements and commentary from or about the book.

Abstract: An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.

Abstract: An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

Abstract: An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

Abstract: A direct current to direct current (DC-DC) converter can include a chip embedded integrated circuit (IC), one or more switches, and an inductor. The IC can be embedded in a PCB. The IC can include driver, switches, and PWM controller. The IC and/or switches can include eGaN. The inductor can be stacked above the IC and/or switches, reducing an overall footprint. One or more capacitors can also be stacked above the IC and/or switches. Vias can couple the inductor and/or capacitors to the IC (e.g., to the switches). The DC-DC converter can offer better transient performance, have lower ripples, or use fewer capacitors. Parasitic effects that prevent efficient, higher switching speeds are reduced. The inductor size and overall footprint can be reduced. Multiple inductor arrangements can improve performance. Various feedback systems can be used, such as a ripple generator in a constant on or off time modulation circuit.

Abstract: A multiphase operation control method comprises configuring a plurality of power phases of a power converter to operate in an interleaved manner by passing a token sequentially among the plurality of power phases, turning on a first power phase after the first power phase possesses the token and receives a trigger signal from a control circuit of the first power phase, passing the token to a second power phase after the first power phase finishes, passing the token sequentially until a last power phase of the plurality of power phases possesses the token and forwarding the token to the first power phase after the last power phase finishes.

Abstract: Disclosed are a floating photovoltaic panel installation structure and a buoyancy body for the installation of the floating photovoltaic panel, which may have excellent strength and buoyancy performance even while having light-weight characteristics, and stably support a photovoltaic panel on the water even during the flowing of a water surface due to waves.

Abstract: Techniques for reducing the specific contact resistance of metal—semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal—group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.

Abstract: An electrical contact structure (an MIS contact) includes one or more conductors (M-Layer), a semiconductor (S-Layer), and an interfacial dielectric layer (I-Layer) of less than 4 nm thickness disposed between and in contact with both the M-Layer and the S-Layer. The I-Layer is an oxide of a metal or a semiconductor. The conductor of the M-Layer that is adjacent to and in direct contact with the I-Layer is a metal oxide that is electrically conductive, chemically stable and unreactive at its interface with the I-Layer at temperatures up to 450° C. The electrical contact structure has a specific contact resistivity of less than or equal to approximately 10?5-10?7 ?-cm2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 2×1019 cm?3 and less than approximately 10?8 ?-cm2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 1020 cm?3.