Abstract: Systems and methods are disclosed for wide frequency range voltage controlled oscillators. For example, an apparatus includes a Voltage Controlled Oscillator (VCO) including a delay cell which includes first and second current sources provided in parallel with one another. The first current source is controlled by a voltage control input connected to a voltage control terminal and the second current source is controlled by a bias voltage input connected to a bias voltage terminal. The first current source provides an alternate current path in the delay cell when the second current source is off. The delay cell is operable to receive an input and produce an output using the alternate current path.

Abstract: A corrugated pizza box is made using a web fed rotary die cutter with the web produced by a corrugator singlefacer that is speed synchronized with the rotary die cutter. The singlefacer produces SemiCorr Singleface Board (SSB) made possible by special corrugating rolls that allow a bottom liner to be bonded to a fluted and creased medium or liner within the singlefacer. This medium or liner has cross flute bond lines that provide in-line stiffness to the two-ply board exiting the singlefacer.

Abstract: During nanoscale manufacture on a substrate, payload active agents are loaded on a delivery platform, with a release layer between the delivery platform and the payload active agent and an encapsulate over the payload active agent. The combined delivery platform, release layer, active agent payload, and encapsulant form a nanoscale drug delivery vehicle for subsequent delivery to a patient. The nanoscale drug delivery vehicle is small enough to permeate through the cell and deliver the payload active agent within the cell via reducing the retaining functionality of the release layer and degrading of the encapsulant. The nanoscale drug delivery vehicle offers a series of improved features including greater control of size, shape, dosage, bioavailability, cell targeting, and release timing.

Abstract: A direct-current to direct-current (DC-DC) converter circuit is provided. The DC-DC converter circuit is capable of generating a DC output voltage in a defined voltage range based on an input voltage. The DC-DC converter circuit can include a modulator circuit, an output filter circuit, and a compensator circuit. In a non-limiting example, the output filter circuit includes an inductor-capacitor (LC) circuit formed by an inductor and a multi-layer ceramic capacitor (MLCC). Notably, the MLCC can produce a variable capacitance in the defined voltage range due to inherent DC bias instability, thus risking stability of the DC-DC converter circuit. As such, a control circuit is configured to determine a configurable transconductance based on feedback of the output voltage and control the compensator circuit to operate accordingly. As such, it may be possible to mitigate the effect of MLCC capacitance variation, thus helping to maintain stability of the DC-DC converter circuit.

Abstract: The present disclosure provides a foldable display back panel and a display terminal. The foldable display back panel includes a rigid support layer and a heat dissipation layer disposed on the rigid support layer. The rigid support layer includes a first planar portion, a second planar portion, and a bending portion. The heat dissipation layer includes a first heat dissipation portion, a second heat dissipation portion, and a bridging portion respectively located on the first planar portion, the second planar portion, and the bending portion. The bridging portion includes a plurality of first thermally conductive members spaced apart from each other and connected to the first heat dissipation portion and the second heat dissipation portion.

Abstract: A means of making a multi ply structural panel by eliminating the top liner in the corrugating process. The present invention is made possible through modification to the corrugating rolls of the singlefacer. The design modification to the rolls involves incorporation of slots that run around the circumference of one roll and mating creasing tools incorporated around the circumference of the other of the corrugated roll set. These slots and creasing tools are incorporated across the existing flutes of the corrugating rolls.

Abstract: A charged particle buncher includes a series of spaced apart electrodes arranged to generate a shaped electric field. The series includes a first electrode, a last electrode and one- or more intermediate electrodes. The charged particle buncher includes a waveform device attached to the electrodes and configured to apply a periodic potential waveform to each electrode independently in a manner so as to form a quasi-electrostatic time varying potential gradient between adjacent electrodes and to cause spatial distribution of charged particles that form a plurality of nodes and antinodes. The nodes have a charged particle density and the antinodes have substantially no charged particle density, and the nodes and the antinodes are formed from a charged particle beam configured to hit the target.

Abstract: A nanowire transistor includes undoped source and drain regions electrically coupled with a channel region. A source stack that is electrically isolated from a gate conductor includes an interfacial layer and a source conductor, and is coaxially wrapped completely around the source region, extending along at least a portion of the source region. A Schottky barrier between the source conductor and the source region is a negative Schottky barrier and a concentration of free charge carriers is induced in the semiconductor source region.

Abstract: A SiC-based MOSFET device and a method for manufacturing the same. Layout design of SiC-based MOSFET devices is optimized, which keeps the JFET region while introducing shielding regions extending into the JFET region, thereby retaining the current flow area of the JFET region to a great extent; each shielding region is connected to the respective well region and extends into the JFET region along a diagonal direction of the cellular structure, effectively shielding high electric field regions when the device is reverse biased, and significantly enhancing the device's reliability. The shielding regions and the well regions are simultaneously formed, requiring no additional process, avoiding increase in complexity and cost of manufacturing. This approach achieves low on-resistance and prevents a decrease in reliability caused by the electric field strength at the bottom of the gate oxide layer exceeding a critical breakdown electric field strength of the gate oxide layer.

Abstract: A direct current to direct current (DC-DC) converter can include a chip embedded integrated circuit (IC), one or more switches, and an inductor. The IC can be embedded in a PCB. The IC can include driver, switches, and PWM controller. The IC and/or switches can include eGaN. The inductor can be stacked above the IC and/or switches, reducing an overall footprint. One or more capacitors can also be stacked above the IC and/or switches. Vias can couple the inductor and/or capacitors to the IC (e.g., to the switches). The DC-DC converter can offer better transient performance, have lower ripples, or use fewer capacitors. Parasitic effects that prevent efficient, higher switching speeds are reduced. The inductor size and overall footprint can be reduced. Multiple inductor arrangements can improve performance. Various feedback systems can be used, such as a ripple generator in a constant on or off time modulation circuit.

Abstract: A power converter can include first, second, third, and fourth switches, and a driver for operating the drive switches to modify an input voltage and provide an output voltage. An AC coupling capacitor can be coupled between the first and fourth switches. The first, second, third, and fourth switches can control current through two inductors. The power converter can have a fifth switch, which can provide a discharge path for discharging the first inductor, the second inductor, and/or the capacitor. Another capacitor can be between the fifth switch and ground. The power converter can provide an output voltage that is at least about ? of the input voltage. The power converter can include resonance circuitry, such as a third inductor, for soft switching the fifth switch.

Abstract: Systems and methods of charge-neutralizing charged particle beams are contemplated, wherein an originating beam is transited through a sequence of slow wave recombination chambers and exposed to neutralizing beams while transit therethrough in order to produce a neutral particle beam. These systems and methods may be seen to be especially suitable for use in spacecraft or other ungrounded environments where the removal of excess charge buildup represents a substantial barrier, and when utilized in a directed energy weapon, may greatly increase the rate at which successive beam pulses may be directed against a target or against multiple targets.

Abstract: A resonant charge pump circuit includes a resonant circuit having a bucket capacitor and a bucket inductor connected in series, and a switching circuit connected to the resonant circuit. The switching circuit switches to a first state that enables current to flow from an input terminal into the resonant circuit to charge the bucket capacitor and the bucket inductor, and switches to a second state that enables current to flow from the resonant circuit to discharge the bucket capacitor and the bucket inductor to an output terminal. The resonant circuit controls current flow into and out from the resonant circuit when the switching circuit switches between the states. The resonant charge pump circuit also includes a timing circuit that controls when the switching circuit switches between the states.

Abstract: An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.

Abstract: A method for preparing a super junction trench MOSFET, comprising: providing a substrate, and forming a first trench in the substrate; depositing an epitaxial portion of a first stage in the first trench while supplying a doped gas and an etching gas, and performing an epitaxial process after stopping supplying the doped gas and the etching gas, wherein impurities in the epitaxial portion of the first stage are diffused to an upper portion of the first trench and to form an epitaxial portion of a second stage with a gradient concentration by utilizing a high-temperature environment of the epitaxial process; forming a well region, a trench gate, and an active region in the substrate at a periphery of the first trench; forming an interlayer dielectric layer covering the column, the trench gate, and the active region; and electrically leading out the column, the trench gate, and the active region.

Abstract: Provided is a probe card, comprising a guide plate and a shielding structure of single-layer or multi-layer. The guide plate comprises an upper surface, a lower surface, and at least one guide hole passing through the upper surface and the lower surface, and the guide hole is provided with an inner wall surface. At least one layer of the shielding structure is made of an electromagnetic absorption material or an electromagnetic reflection material, and the shielding structure is not connected to a ground. Each layer of the shielding structure is formed on the inner wall surface of the guide hole by means of atomic layer deposition or atomic layer etching, and a thickness of each layer is less than 1000 nm.

Abstract: Embodiments of the present application provide a GRPC-based chip test method, a GRPC-based chip test apparatus, and a storage medium. The GRPC-based chip test method comprises: determining a number of to-be-tested chips that actually need to be tested among to-be-tested chips, and issuing a corresponding number of remote instrument call requests according to the number of to-be-tested chips that actually need to be tested; acquiring each of the remote instrument call requests based on a GRPC protocol; and sorting all the remote instrument call requests to form a request execution sequence table, and controlling the test instrument to sequentially test the to-be-tested chips that actually need to be tested according to the request execution sequence table.

Abstract: A system is provided that predicts motor wear and failures before they occur. Telemetry data from motors in a motor application is collected and predictive algorithms are used to determine when a motor is aging and when it may fail. Identifying a potential failure in these types of applications can help mitigate risk of other equipment failures and realize cost savings. In one example, a motor aging detection system is provided that includes one or more DC motors, and a motor controller coupled to each motor. The motor controller reads three phase currents from each motor and converts the phase currents to digital values, calculates telemetry data including applied voltages, back electric-motive force, inductance, and resistance of each motor at periodic intervals, stores this telemetry data for each motor in a memory. An age detection circuit retrieves this information from the memory and determines age factors of the motor.

Abstract: A means of making a multi ply structural panel by eliminating the top liner in the corrugating process. The present invention is made possible through modification to the corrugating rolls of the singlefacer. The design modification to the rolls involves incorporation of slots that run around the circumference of one roll and mating creasing tools incorporated around the circumference of the other of the corrugated roll set. These slots and creasing tools are incorporated across the existing flutes of the corrugating rolls.