Abstract: A charged particle buncher includes a series of spaced apart electrodes arranged to generate a shaped electric field. The series includes a first electrode, a last electrode and one or more intermediate electrodes. The charged particle buncher includes a waveform device attached to the electrodes and configured to apply a periodic potential waveform to each electrode independently in a manner so as to form a quasi-electrostatic time varying potential gradient between adjacent electrodes and to cause spatial distribution of charged particles that form a plurality of nodes and antinodes. The nodes have a charged particle density and the antinodes have substantially no charged particle density, and the nodes and the antinodes are formed from a charged particle beam configured to hit the target.

Abstract: The present disclosure relates to an LED lighting device for strawberry seedling raising. The LED lighting device for strawberry seedling raising according to an exemplary embodiment of the present disclosure includes: a light emitting unit composed of a first light emitting part composed of a red region wavelength emission LED and a blue region wavelength emission LED and a second light emitting part composed of the red region wavelength emission LED and an infrared region wavelength emission LED; and a control part for controlling the light emitting unit to manage a strawberry seedling raising, and controlling each LED included in the first light emitting part or the second light emitting part to be turned on/off based on a preset seedling raising mode.

Abstract: A display panel and a manufacturing method thereof are disclosed. The display panel includes a display device and an anti-reflective layer disposed on the display device. The display device includes a plurality of sub-pixel areas distributed in an array manner. The anti-reflected layer includes a plurality of organic light-transmissive thin films corresponding to the sub-pixel areas. A plurality of inorganic nanoparticles are doped in the organic light-transmissive thin films. The inorganic nanoparticles at a side of the organic light-transmissive thin films away from the display device protrude from a surface of the organic light-transmissive thin films to form a plurality of nano moth-eye structures.

Abstract: One or more chip-embedded integrated voltage regulators (“CEIVR's”) are configured to provide power to a circuit or chip such as a CPU or GPU and meet power delivery specifications. The CEIVR's, circuit or chip, and power delivery pathways can be included within the same package. The CEIVR's can be separate from the circuit or chip.

Abstract: Disclosed herein is an overwater photovoltaic panel installation structure having an environment-friendly marine-farm-type mooring anchor module that supports a photovoltaic panel on the water and includes a growth space where aquatic organisms are growable. The environment-friendly marine-farm-type mooring anchor module including a growth space where aquatic organisms are growable, includes an anchor module body defining an external appearance thereof, a frame section disposed inside the anchor module body and made of a more rigid material than the anchor module body, and a connection section exposed through an upper surface of the anchor module body and having both lower ends coupled to the frame section. The anchor module body has a plurality of growth space sections recessed from at least one surface thereof to provide a growth space for aquatic organisms.

Abstract: A die can be applied to a front conductive layer. Openings can be formed in the conductive layer over contact points on the die. The openings can be filled with a conductive material to electrically couple the conductive layer to the contact points on the die. The front conductive layer can be etched to form a first conductive pattern. Conductive standoffs can be formed on portions of the front conductive layer. An additional front conductive layer can be laminated onto the front side. Openings can be formed in the additional front conductive layer over the standoffs. The openings can be filled with a conductive material to electrically couple the additional conductive layer to the underlying standoffs. The additional conductive layer can be etched to form a second conductive pattern.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor structure is formed on a first surface of a silicon substrate. The semiconductor structure has a first surface facing the silicon substrate. At least one outer circuit is bonded to the semiconductor structure. A molding compound layer is formed covering a second surface of the silicon substrate. A part of the molding compound layer is removed for exposing the silicon substrate. The silicon substrate is removed for exposing the first surface of the semiconductor structure.

Abstract: Techniques for reducing the specific contact resistance of metal-semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal-group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.

Abstract: A charged particle buncher includes a series of spaced apart electrodes arranged to generate a shaped electric field. The series includes a first electrode, a last electrode and one or more intermediate electrodes. The charged particle buncher includes a waveform device attached to the electrodes and configured to apply a periodic potential waveform to each electrode independently in a manner so as to form a quasi-electrostatic time varying potential gradient between adjacent electrodes and to cause spatial distribution of charged particles that form a plurality of nodes and antinodes. The nodes have a charged particle density and the antinodes have substantially no charged particle density, and the nodes and the antinodes are formed from a charged particle beam with an energy less than or equal to 500 keV.

Abstract: A semiconductor device includes at least one active region, a first dielectric layer, a gate structure, and an air void. The active region includes a III-V compound semiconductor layer. The first dielectric layer is disposed on the active region. The gate structure is disposed on the active region, and at least a part of the gate structure is disposed in the first dielectric layer. The air void is disposed in the first dielectric layer, and at least a part of the air void is disposed at two opposite sides of the gate structure in a horizontal direction.

Abstract: A direct current to direct current (DC-DC) converter can include a chip embedded integrated circuit (IC), one or more switches, and an inductor. The IC can be embedded in a PCB. The IC can include driver, switches, and PWM controller. The IC and/or switches can include eGaN. The inductor can be stacked above the IC and/or switches, reducing an overall footprint. One or more capacitors can also be stacked above the IC and/or switches. Vias can couple the inductor and/or capacitors to the IC (e.g., to the switches). The DC-DC converter can offer better transient performance, have lower ripples, or use fewer capacitors. Parasitic effects that prevent efficient, higher switching speeds are reduced. The inductor size and overall footprint can be reduced. Multiple inductor arrangements can improve performance. Various feedback systems can be used, such as a ripple generator in a constant on or off time modulation circuit.

Abstract: An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.

Abstract: The present disclosure provides for a kit-less pick and place handler which conducts thermal testing of at least one device. An exemplary handler includes a thermal soak plate, a first prime mover, a second prime mover, a test site actuator, and a test contactor. The thermal soak plate can receive devices and maintain an accurate position of the devices using a friction between the thermal soak plate and the device. The test contactor can electrically contact the device. The first prime mover can place the device on the thermal soak plate. The second prime mover can carry the device to the test contactor, hold the device during thermal testing, and move the device from the test contactor. The test site actuator can exert force on the second prime mover during thermal testing.

Abstract: A nanowire transistor includes undoped source and drain regions electrically coupled with a channel region. A source stack that is electrically isolated from a gate conductor includes an interfacial layer and a source conductor, and is coaxially wrapped completely around the source region, extending along at least a portion of the source region. A Schottky barrier between the source conductor and the source region is a negative Schottky barrier and a concentration of free charge carriers is induced in the semiconductor source region.

Abstract: The present disclosure provides for a kit-less pick and place handler which conducts thermal testing of at least one device. An exemplary handler includes a thermal soak plate, a first prime mover, a second prime mover, a test site actuator, and a test contactor. The thermal soak plate can receive devices and maintain an accurate position of the devices using a friction between the thermal soak plate and the device. The test contactor can electrically contact the device. The first prime mover can place the device on the thermal soak plate. The second prime mover can carry the device to the test contactor, hold the device during thermal testing, and move the device from the test contactor. The test site actuator can exert force on the second prime mover during thermal testing.

Abstract: A power switch circuit includes an internal node; a first field-effect transistor including a first drain, a first gate and a first source; a second field-effect transistor including a second drain, a second gate and a second source, wherein the first drain is coupled to a voltage supply terminal, the first gate is coupled to the second source, the first source and the second drain are coupled to the internal node, and the second source is coupled to a ground; and a regulating circuit is coupled to the internal node, wherein the regulating circuit is configured to regulate a voltage value of the internal node after the power switch circuit is activated.

Abstract: Methods and apparatus for selecting operating modes in a device are disclosed. In an embodiment, a method includes powering on a device that is configured to operate in safe and normal operating modes, detecting whether the device enters the normal operating mode within a time interval, and enabling the device to operate in the safe operating mode when the device does not enter the normal operating mode within the time interval. In an embodiment, an apparatus includes a power signal controller that powers on a device that is configured to operate in safe and normal operating modes, a state machine that detects whether the device enters the normal operating mode within a time interval, and a control signal controller that enables the device to operate in the safe operating mode when the device does not enter the normal operating mode within the time interval.

Abstract: A system is provided that predicts motor wear and failures before they occur. Telemetry data from motors in a motor application is collected and predictive algorithms are used to determine when a motor is aging and when it may fail. Identifying a potential failure in these types of applications can help mitigate risk of other equipment failures and realize cost savings. In one example, a motor aging detection system is provided that includes one or more DC motors, and a motor controller coupled to each motor. The motor controller reads three phase currents from each motor and converts the phase currents to digital values, calculates telemetry data including applied voltages, back electric-motive force, inductance, and resistance of each motor at periodic intervals, stores this telemetry data for each motor in a memory. An age detection circuit retrieves this information from the memory and determines age factors of the motor.

Abstract: A resonant charge pump circuit includes a resonant circuit having a bucket capacitor and a bucket inductor connected in series, and a switching circuit connected to the resonant circuit. The switching circuit switches to a first state that enables current to flow from an input terminal into the resonant circuit to charge the bucket capacitor and the bucket inductor, and switches to a second state that enables current to flow from the resonant circuit to discharge the bucket capacitor and the bucket inductor to an output terminal. The resonant circuit controls current flow into and out from the resonant circuit when the switching circuit switches between the states. The resonant charge pump circuit also includes a timing circuit that controls when the switching circuit switches between the states.

Abstract: An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.