Patents Assigned to Semiconductor Components Industries
  • Patent number: 11943477
    Abstract: Various embodiments of the present technology may comprise methods and apparatus for successive intra block prediction. Methods and apparatus for successive intra block prediction may comprise a matching decoder to generate data that replicates the internal state and/or the decompressed data at the decoder. The apparatus may further comprise a prediction module that utilizes the replicated data to make predictions. The apparatus may then utilize the predicted data and the original, input source data to determine a difference value and encode the difference value.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: March 26, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Marko Mlinar
  • Patent number: 11942366
    Abstract: Implementations of die singulation systems and related methods may include forming a plurality of die on a first side of a substrate, forming a seed layer on a second side of a substrate opposite the first side of the substrate, using a shadow mask, applying a mask layer over the seed layer, forming a backside metal layer over the seed layer, removing the mask layer, and singulating the plurality of die included in the substrate through removing substrate material in the die street and through removing seed layer material in the die street.
    Type: Grant
    Filed: October 3, 2022
    Date of Patent: March 26, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • Patent number: 11943553
    Abstract: An image sensor may include an array of image sensor pixels. Pixel control circuitry may provide control signals to the array of image sensor pixels. The pixel control circuitry may include a plurality of driver units that each generate a control signal for a different set of image sensor pixels. The control signal generated by each of the driver units may be delayed relative to each other. A voltage-controlled delay line may provide delayed outputs to each of the driver units. Delay lock circuitry coupled to the voltage-controlled delay line may fix the delay exhibited across the delay line using corresponding global and local bias voltages provided to each of the inverters in the delay line.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: March 26, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Gal Fadida
  • Patent number: 11943542
    Abstract: An imaging device may include single-photon avalanche diodes (SPADs). To improve the sensitivity and signal-to-noise ratio of the SPADs, photon detection efficiency (PDE) may be increased. However increased photon detection efficiency may result in a decreased saturation rate and lower than desired dynamic range. To increase the dynamic range, a SPAD-based semiconductor device may operate with multiple sub-exposures. During the first sub-exposure, an over-bias voltage may be set to a first voltage level so that the SPADs have a first photon detection efficiency. During the second sub-exposure, the over-bias voltage may be set to a second voltage level so that the SPADs have a second photon detection efficiency that is different than the first photon detection efficiency. Image data from the first and second sub-exposures may then be combined into a single high dynamic range depth map.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: March 26, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Salvatore Gnecchi
  • Patent number: 11942327
    Abstract: A method of singulating a silicon carbide (SiC) semiconductor wafer can include defining a cut within the silicon carbide (SiC) semiconductor wafer by performing a partial dicing operation where the SiC semiconductor wafer is aligned along a plane and the cut has a depth less than a first thickness of the SiC semiconductor wafer. The cut is aligned along a vertical direction orthogonal to the plane such that a portion of the SiC semiconductor wafer has a second thickness that extends between a bottom of the cut and an outer surface of the SiC semiconductor wafer. The method can further include defining a cleave, by performing a cleaving operation, through the portion of the SiC semiconductor wafer having the second thickness. The cleave can be aligned with the cut and extending to the outer surface of the SiC semiconductor wafer.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: March 26, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Aira Lourdes Villamor
  • Patent number: 11940864
    Abstract: A multiphase power supply including a controller and phases can respond to a drop in load level by reducing all but one active phase to reduce power consumption. If the load level drops further, further reduction of the power consumption could be achieved by reducing, changing, or disabling the functions of some circuits within the active phase during these conditions. Estimating these conditions, however, may be difficult for a controller when the communication between the controller and the phase is limited. The disclosure describes an active phase that estimates a state of the load based on a sensed output current and a pulse width modulation control signal. The active phase may change its operating mode to match the estimated state of the load so that lighter load conditions consume less power. Furthermore, the idle phase(s) may nearly turn off all function except PWM detection to save power. Because this mode change is local to the phase, no additional communication with the controller is required.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: March 26, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Han Zou
  • Patent number: 11942326
    Abstract: A process to form a HEMT can have a gate electrode layer that initially has a plurality of spaced-apart doped regions. In an embodiment, any of the spaced-apart doped regions can be formed by depositing or implanting p-type dopant atoms. After patterning, the gate electrode can include an n-type doped region over the p-type doped region. In another embodiment a barrier layer can underlie the gate electrode and include a lower film with a higher Al content and thinner than an upper film. In a further embodiment, a silicon nitride layer can be formed over the gate electrode layer and can help to provide Si atoms for the n-type doped region and increase a Mg:H ratio within the gate electrode. The HEMT can have good turn-on characteristics, low gate leakage when in the on-state, and better time-dependent breakdown as compared to a conventional HEMT.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: March 26, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Petr Kostelnik, Tomas Novak, Peter Coppens, Peter Moens, Abhishek Banerjee
  • Patent number: 11942498
    Abstract: An imaging device may include a plurality of single-photon avalanche diode (SPAD) pixels. The SPAD pixels may be overlapped by square toroidal microlenses to direct light incident on the pixels onto photosensitive regions of the pixels. The square toroidal microlenses may be formed as first and second sets of microlenses aligned with every other SPAD pixel and may allow the square toroidal microlenses to be formed without gaps between adjacent lenses. Additionally or alternatively, a central portion of each square toroidal microlenses may be filled by a fill-in microlens. Together, the square toroidal microlenses and the fill-in microlenses may form convex microlenses over each SPAD pixel. The fill-in microlenses may be formed from material having a higher index of refraction than material that forms the square toroidal microlenses.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: March 26, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Marc Allen Sulfridge, Byounghee Lee, Ulrich Boettiger
  • Patent number: 11942369
    Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: March 26, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Shutesh Krishnan, Sw Wei Wang, Ch Chew, How Kiat Liew, Fui Fui Tan
  • Publication number: 20240097631
    Abstract: The operational amplifier disclosed includes an input stage configured to receive power from a floating supply in a low voltage range that can float according to the common mode voltage at the input. The floating supply facilitates the use of low voltage components that can improve the precision of the operational amplifier by lowering the offset voltage. The input stage includes a first gain stage including field effect transistors and a second gain stage using bipolar transistors. The gain stages can be implemented differently to accommodate different applications and fabrication capabilities.
    Type: Application
    Filed: March 14, 2022
    Publication date: March 21, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Catalin Ionut PETROIANU
  • Publication number: 20240097555
    Abstract: A driver is suitable for use with a gallium nitride (GaN) power stage, and includes a voltage regulator and a high side driver. The voltage regulator provides a boot voltage between first and second terminals thereof that varies within a range between a turn-on voltage of a GaN transistor, and a safe voltage limit between a gate and a source thereof throughout an active time of said GaN transistor. The high side driver has an input for receiving a high side drive signal, an output for coupling to said gate of said GaN transistor, a power supply terminal coupled to said first terminal of said voltage regulator, and a ground terminal for coupled to said second terminal of said voltage regulator.
    Type: Application
    Filed: September 21, 2022
    Publication date: March 21, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Karel PTACEK, Dhruv CHOPRA
  • Publication number: 20240097429
    Abstract: Illustrative GFCI devices and methods maintain safety while reducing the risk of unnecessary interruptions. One illustrative GFCI circuit includes: a first operational amplifier configured to couple to a first current transformer that senses a net current through multiple power conductors, the first operational amplifier configured to convert a signal current from a signal terminal of the first current transformer to a signal voltage, the signal voltage having an inverse dependence on frequency; an analog to digital converter configured to provide samples of the signal voltage; and a controller configured to interrupt at least one of the multiple power conductors when an magnitude measurement derived from the samples exceeds a frequency-independent and/or phase-independent threshold a predetermined number of times or for a predetermined time period.
    Type: Application
    Filed: August 15, 2023
    Publication date: March 21, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Rishi Pratap SINGH, Colton JENSEN, Yixin SONG, Seunghan BACK
  • Publication number: 20240096734
    Abstract: A semiconductor device module may include a leadframe spacer that provides the functions of both a leadframe and a spacer, while enabling a double-sided cooling configuration. Such a leadframe spacer may include a leadframe surface that provides a die attach pad (DAP) that is shared by at least two semiconductor devices. The leadframe spacer may include at least one downset, where the semiconductor devices may be attached within a recess defined by the at least one downset. A first substrate may be connected to a first side of the leadframe. A second substrate may be connected to downset surfaces of the at least one downset, and positioned for further connection to the semiconductor devices in a double-sided assembly.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 21, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Tzu-Hsuan CHENG, Yong LIU, Liangbiao CHEN
  • Publication number: 20240094385
    Abstract: An illustrative controller includes: a transmitter to drive the acoustic transducer to generate a series of acoustic bursts; a receiver coupled to the acoustic transducer to sense a response for each acoustic burst in the series; and a processing circuit to derive output data from said responses in part by determining a difference between one of the responses and at least a portion of another one of the responses. Another illustrative controller includes: a transmitter to drive the acoustic transducer to generate a series of acoustic bursts with signature sequence of frequency displacements; a receiver coupled to the acoustic transducer to sense a response for each acoustic burst in the series; and a processing circuit to derive output data from said responses in part by suppressing any peaks not conforming to the signature sequence.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Marek HUSTAVA, Pavel KOSTELNIK
  • Patent number: 11935546
    Abstract: Audio streaming devices, systems, and methods may employ adaptive differential pulse code modulation (ADPCM) techniques providing for optimum performance even while ensuring robustness against transmission errors. One illustrative device includes: a difference element that produces a sequence of prediction error values by subtracting predicted values from audio samples; a scaling element that produces scaled error values by dividing each prediction error by a corresponding envelope estimate; a quantizer that operates on the scaled error values to produce quantized error values; a multiplier that uses the corresponding envelope estimates to produce reconstructed error values; a predictor that produces the next audio sample values based on the reconstructed error values; and an envelope estimator.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: March 19, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Erkan Onat
  • Patent number: 11935817
    Abstract: A method includes disposing a plurality of active solder pads and at least one mechanical support solder pad on the substrate. The plurality of active solder pads provide areas for mechanical bonding of the substrate to at least one device contact pad disposed on a semiconductor die. The at least one mechanical support solder pad provides an area for mechanical bonding of the substrate to at least one dummy device contact pad disposed on the semiconductor die. The method further includes mechanically bonding the substrate to the semiconductor die by forming solder joints between the plurality of active solder pads and the at least one device contact pad, and between the at least one mechanical support pad and the at least one dummy device contact pad.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: March 19, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yusheng Lin, Jerome Teysseyre, Huibin Chen
  • Patent number: 11936385
    Abstract: In some aspects, the techniques described herein relate to a system on a chip (SoC) including a first clock divider configured to: receive an oscillator signal at a first frequency; produce, based on the oscillator signal: a first clock signal at the first frequency; and a second clock signal at a second frequency, the second frequency being a division of the first frequency. The first clock divider can selectively provide the first clock signal or the second clock signal as a first output clock signal based on a scaling configuration signal. The first clock divider can produce a frequency indication signal indicating, in combination with the first output clock signal, a start of a new clock period of the second clock signal. The SoC can include a second clock divider configured to provide a second clock output signal based on the first output clock signal and the frequency indication signal.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: March 19, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Ivo Leonardus Coenen
  • Publication number: 20240088007
    Abstract: A package includes a first direct bonded metal (DBM) substrate, a first semiconductor die disposed on a top surface of the first DBM substrate, a second DBM substrate disposed at a height above the first DBM substrate, and a second semiconductor die disposed on a top surface of the second DBM substrate. A wire bond is made between the first semiconductor die disposed on the top surface of the first DBM substrate and the second semiconductor die disposed on the top surface of the second DBM substrate.
    Type: Application
    Filed: September 13, 2022
    Publication date: March 14, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jonghwan BAEK, Jeonghyuk PARK, Seungwon IM, Keunhyuk LEE, Dukyong LEE
  • Publication number: 20240088853
    Abstract: The techniques described herein relate to a circuit including an operational amplifier that includes a differential amplifier, a capacitor, and an output stage. The differential amplifier includes a first input and a second input. The output stage is configured to generate an output voltage. The circuit includes a slew-rate boost circuitry connected to the operational amplifier. The slew-rate boost circuitry is configured to detect a voltage differential between the first input and the second input and apply, at an output of the differential amplifier, a boost current to charge the capacitor during a period of time in which the output voltage increases or decreases to a target voltage level.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 14, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Catalin Ionut PETROIANU, Alexandra-Oana PETROIANU
  • Publication number: 20240090130
    Abstract: A semiconductor device package may include a substrate having an insulating layer with a patterned conductive layer formed thereon, the patterned conductive layer including at least a first pattern portion and a second pattern portion. The semiconductor device package may include a leadframe having a lead that is soldered to the substrate with solder provided in an opening between the first pattern portion and the second pattern portion and with the lead inserted into the opening.
    Type: Application
    Filed: September 13, 2022
    Publication date: March 14, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Chad CHEN, Jiahui LIU, Wuxing XIA, Jingyan LIU