Patents Assigned to Semiconductor Components Industries
  • Publication number: 20240071860
    Abstract: In a general aspect, a package includes a semiconductor die disposed between a first high voltage isolation carrier and a second high voltage isolation carrier. The semiconductor die is thermally coupled to the first high voltage isolation carrier. The package also includes a molding material disposed in a space between the semiconductor die and the first high voltage isolation carrier, and a conductive spacer disposed between the semiconductor die and the second high voltage isolation carrier. The conductive spacer is thermally coupled to semiconductor die and to the second high voltage isolation carrier. A longitudinal dimension of the conductive spacer is greater than a longitudinal dimension of the semiconductor die. The molding material encapsulates the semiconductor die and the conductive spacer.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yusheng LIN, Jerome TEYSSEYRE
  • Patent number: 11916619
    Abstract: A tuning circuit for a near-field magnetic induction (NFMI) system suitable for near field communication (NFC) is disclosed. The NFMI system includes a tuning circuit that is configured to measure a phase across a series capacitor coupled between a resonant circuit and a transmit circuit in order to determine a resonant condition of the resonant circuit. When the resonant condition is above resonance or below resonance, the tuning circuit can tune an adjustable capacitor of the resonant circuit. The tuning can continue until the phase measurement indicates that the resonant circuit is at resonance. The phase-based tuning allows for the tuning to operate continuously and concurrently with NFC.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: February 27, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Gareth Pryce Weale
  • Patent number: 11917272
    Abstract: An imaging device may have an array of image pixels that includes red, green, blue, and infrared pixels. The imaging device may include a dual-band filter that allows transmission of light in the visible band and in the near-infrared band and may include color processing circuitry that produces a color image with marked infrared regions. The color processing circuitry may include a standard color processing pipeline with a color correction matrix that produces a tone-mapped standard red, green, and blue image and may include infrared marking circuitry. The infrared marking circuitry may include hue angle determination circuitry, cell means determination circuitry, and near-infrared determination circuitry that determine portions of the image with high infrared reflectance to be marked. The infrared-marked tone-mapped standard red, green, and blue image may be output to a machine vision system to identify objects in the imaged scene with high infrared reflection.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: February 27, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Orit Skorka, Paul James Kane, David Wayne Jasinski
  • Publication number: 20240064944
    Abstract: A package includes a power electronics module disposed between a first bracket and a second bracket with the power electronics module covering openings in the first bracket and the second bracket. Leak-proof joints are formed between surfaces of the power electronics module and the first bracket and the second bracket. A first cover beam is disposed on, and joined to, the first bracket to enclose a first cooling fluid channel for cooling fluid flow over the power electronics module. A second cover beam is disposed on, and joined to, the second bracket to enclose a second cooling fluid channel for cooling fluid flow over the power electronics module. The package includes end connectors that have input and output ports for cooling fluid flow through the first cooling fluid channel and the second cooling fluid channel.
    Type: Application
    Filed: August 2, 2023
    Publication date: February 22, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Roveendra PAUL, Hyungsoo KIM
  • Publication number: 20240061800
    Abstract: Accordingly, there is disclosed herein host device and bus communication method that enables fast sensor device reinitialization that minimizes outage time associated with an unexpected device reset. One illustrative bus communication method includes: providing each of one or more slave devices with a dynamically-determined bus address; querying each of the dynamically-determined bus addresses to obtain a unique device identifier associated with that dynamically-determined bus address; receiving a sequence of data frames each having time-division multiplexed data from the one or more slave devices; and between data frames in the sequence, checking to determine whether any of the one or more slave devices has been reset.
    Type: Application
    Filed: February 1, 2023
    Publication date: February 22, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Marek HUSTAVA
  • Patent number: 11908840
    Abstract: Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: February 20, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Chee Hiong Chew, Atapol Prajuckamol, Stephen St. Germain, Yusheng Lin
  • Patent number: 11906555
    Abstract: Methods and systems for emulating high side current of a power switch including low and high side switches. The method includes generating, with a low side current sensor, a low side current signal for the low side switch when the power switch is in a low state. The method also includes generating, with a first transconductance amplifier, an emulated current signal based on an input voltage of the power switch. The method further includes generating, with a buffer, a fixed reference voltage by sampling the low side current signal when the power switch changes from the low state to a high state. The method also includes generating, with a capacitor, an emulated voltage based on the emulated current signal and the fixed reference voltage. The method further includes, generating, with a second transconductance amplifier, a high side current signal for the high side switch based on the emulated voltage.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: February 20, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Mahbub Hasan, Yue Hung Tang
  • Patent number: 11908826
    Abstract: A clip preform includes a die contact portion and an aligner structure. An intermediate portion connects the die contact portion to a lead contact portion in the aligner structure. The die contact portion is configured to contact a semiconductor die. The aligner structure is configured to attach the lead contact portion to a lead post. The die contact portion, the intermediate portion, and the aligner structure form a structure of a primary clip for connecting the semiconductor die to the lead post. The clip preform is severable by removing parts of the die contact portion and the intermediate portion of the clip preform to form a secondary clip for connecting the semiconductor die to the lead post. The aligner structure, a remaining part of the die contact portion, and a remaining part of the intermediate portion of the clip preform form a structure of the secondary clip.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: February 20, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Keunhyuk Lee, Jerome Teysseyre, Tiburcio A. Maldo
  • Patent number: 11908699
    Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and into the plurality of notches; forming a cavity into each of a plurality of semiconductor die included in the semiconductor substrate; applying a backmetal into the cavity in each of the plurality of semiconductor die included in the semiconductor substrate; and singulating the semiconductor substrate through the organic material into a plurality of semiconductor packages.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: February 20, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Francis J. Carney, Chee Hiong Chew, Soon Wei Wang, Eiji Kurose
  • Publication number: 20240051089
    Abstract: Implementations of a clamp finger may include a first portion including at least one tip configured to clamp a substrate against an anvil during a bonding operation; and a second portion including a first opening therethrough configured to permit coupling of the second portion with a clamping bridge. The first portion may be slidably coupled with the second portion through a rail and the first portion may include an opening therethrough configured to receive a screw that fixedly couples the at least one tip of the first portion at a desired position relative to the second portion.
    Type: Application
    Filed: August 12, 2022
    Publication date: February 15, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Sen SUN, Kun FENG, Hu CHENG, Naima WANG
  • Publication number: 20240055503
    Abstract: In an example, a semiconductor device includes a region of semiconductor material, a first dielectric over the region of semiconductor material, a first gate conductor over a first portion of the first dielectric, and a second gate conductor over a second portion of the first dielectric and laterally spaced apart from the first gate conductor. A first conductor is coupled to the first gate conductor and a second conductor coupled to the second gate conductor and laterally separated from the first conductor by a first spacing. A second dielectric is within the first spacing. The first conductor and the second conductor are laterally capacitively coupled, the first gate conductor is vertically capacitively coupled to the region of semiconductor material, and the second gate conductor is vertically capacitively coupled to the region of semiconductor material.
    Type: Application
    Filed: August 10, 2022
    Publication date: February 15, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Arash ELHAMI KHORASANI, Mark GRISWOLD
  • Publication number: 20240055298
    Abstract: Described implementations include a contaminant-free plasma singulation process, in which residues of materials used during plasma singulation are fully removed from sidewalls of a resulting semiconductor die, without damaging the semiconductor die. From such a contaminant-free plasma singulation process, a semiconductor die may be manufactured. The semiconductor die may include a first plurality of sidewall recesses formed in a sidewall of a substrate of the semiconductor die between a first surface and a second surface of the substrate, each having at most a first depth, as well as a second plurality of sidewall recesses formed in the sidewall of the substrate and disposed between the first plurality of sidewall recesses and the second surface, each having at least a second depth that is greater than the first depth.
    Type: Application
    Filed: October 20, 2023
    Publication date: February 15, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: JeongPyo HONG, Mohd Akbar MD SUM, Gordon M. GRIVNA
  • Publication number: 20240055334
    Abstract: In a general aspect, an electronic device assembly includes a circuit including at least one semiconductor die, and a signal lead electrically coupled with the circuit. The signal lead has a hole defined therethrough. The assembly further includes an electrically conductive signal pin holder disposed in the hole of the signal lead. The electrically conductive signal pin holder is electrically coupled with the signal lead. The assembly also includes a molding compound encapsulating, at least, the circuit; a portion of the signal lead including the hole; and a portion of the electrically conductive signal pin holder. An open end of the electrically conductive signal pin holder is accessible outside the molding compound.
    Type: Application
    Filed: July 19, 2023
    Publication date: February 15, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Seungwon IM, Oseob JEON, Jihwan KIM, Dongwook KANG
  • Publication number: 20240055537
    Abstract: An imaging device may include single-photon avalanche diodes (SPADs). To improve the sensitivity and signal-to-noise ratio of the SPADs, light scattering structures may be formed in the semiconductor substrate to increase the path length of incident light through the semiconductor substrate. To mitigate crosstalk, multiple rings of isolation structures may be formed around the SPAD. An outer deep trench isolation structure may include a metal filler such as tungsten and may be configured to absorb light. The outer deep trench isolation structure therefore prevents crosstalk between adjacent SPADs. Additionally, one or more inner deep trench isolation structures may be included. The inner deep trench isolation structures may include a low-index filler to reflect light and keep incident light in the active area of the SPAD.
    Type: Application
    Filed: October 25, 2023
    Publication date: February 15, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Marc Allen SULFRIDGE, Anne DEIGNAN, Nader JEDIDI, Michael Gerard KEYES
  • Publication number: 20240056044
    Abstract: The operational amplifier disclosed includes an input stage configured to receive power from a floating supply circuit in in a low voltage range that can float according to the common mode voltage at the input. The low voltage supply facilitates the use of low voltage components that can improve the precision of the operational amplifier by lowering the offset voltage. The input stage utilizes a first gain block and a second gain block. The first gain block is configured to have a low offset voltage while the second gain h block is configured to have a high gain. Dividing these aspects over separate gain blocks improves the precision and noise performance of the operational amplifier. The operational amplifier has high gain at low frequencies and at high frequencies due to a topology that combines a low gain, high bandwidth path with a high gain, low bandwidth path at the output.
    Type: Application
    Filed: February 3, 2022
    Publication date: February 15, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Catalin Ionut PETROIANU
  • Patent number: 11898845
    Abstract: In a general aspect, a micromachined gyroscope can include a substrate and a static mass suspended in an x-y plane over the substrate by a plurality of anchors attached to the substrate. The static mass can be attached to the anchors by anchor suspension flexures. The micromachined gyroscope can include a dynamic mass surrounding the static mass and suspended from the static mass by one or more gyroscope suspension flexures.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: February 13, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Cenk Acar, Brenton Simon, Sandipan Maity
  • Patent number: 11899106
    Abstract: An acoustic distance measurement circuit includes a transmitter, a receiver, and a controller. The transmitter has an output adapted to be coupled to an acoustic transducer for providing a selected one of an amplitude-modulation (AM) signal in an AM mode and a chirp signal in a chirp mode. The receiver has an input adapted to be coupled to the acoustic transducer, and an output for providing a digital received signal. The controller is operative during a first measurement period to: place the transmitter into one of the AM mode and the chirp mode using a first channel, selectively detect a direct echo in the first channel of the digital received signal of the one of the AM signal and the chirp signal, and selectively detect an indirect echo in a second channel of the digital received signal of another one of the AM signal and the chirp signal.
    Type: Grant
    Filed: October 5, 2022
    Date of Patent: February 13, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Marek Hustava, Pavel Kostelnik
  • Patent number: 11901184
    Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; stress relief etching the second side of the semiconductor substrate; applying a backmetal over the second side of the semiconductor substrate; removing one or more portions of the backmetal through jet ablating the second side of the semiconductor substrate; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: February 13, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Francis J. Carney, Chee Hiong Chew, Soon Wei Wang, Eiji Kurose
  • Patent number: 11901309
    Abstract: In general aspect, a semiconductor device package can include a substrate and a semiconductor die disposed on and coupled with the substrate. The semiconductor device package can further include a leadframe having an indentation defined therein, at least a portion of the indentation being disposed on and coupled with the semiconductor die via a conductive adhesive.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: February 13, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Seungwon Im, Oseob Jeon
  • Publication number: 20240047498
    Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side and an active area on the second side of the die. The semiconductor packages may also include two or more bumps coupled to two or more die pads on a second side of the die. The semiconductor packages may include an optically transmissive lid coupled to the semiconductor die through an adhesive, two or more bumps, and a first redistribution layer (RDL). The semiconductor package may include a second redistribution layer (RDL) coupled with the first RDL on the second side of the semiconductor die. The second RDL may extend to the first side of the semiconductor die. The first RDL may extend to an edge of the semiconductor die.
    Type: Application
    Filed: October 19, 2023
    Publication date: February 8, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Shou-Chian HSU