Abstract: Audio streaming devices, systems, and methods may employ adaptive differential pulse code modulation (ADPCM) techniques providing for optimum performance even while ensuring robustness against transmission errors. One illustrative device includes: a difference element that produces a sequence of prediction error values by subtracting predicted values from audio samples; a scaling element that produces scaled error values by dividing each prediction error by a corresponding envelope estimate; a quantizer that operates on the scaled error values to produce quantized error values; a multiplier that uses the corresponding envelope estimates to produce reconstructed error values; a predictor that produces the next audio sample values based on the reconstructed error values; and an envelope estimator.

Abstract: A method includes disposing a plurality of active solder pads and at least one mechanical support solder pad on the substrate. The plurality of active solder pads provide areas for mechanical bonding of the substrate to at least one device contact pad disposed on a semiconductor die. The at least one mechanical support solder pad provides an area for mechanical bonding of the substrate to at least one dummy device contact pad disposed on the semiconductor die. The method further includes mechanically bonding the substrate to the semiconductor die by forming solder joints between the plurality of active solder pads and the at least one device contact pad, and between the at least one mechanical support pad and the at least one dummy device contact pad.

Abstract: In some aspects, the techniques described herein relate to a system on a chip (SoC) including a first clock divider configured to: receive an oscillator signal at a first frequency; produce, based on the oscillator signal: a first clock signal at the first frequency; and a second clock signal at a second frequency, the second frequency being a division of the first frequency. The first clock divider can selectively provide the first clock signal or the second clock signal as a first output clock signal based on a scaling configuration signal. The first clock divider can produce a frequency indication signal indicating, in combination with the first output clock signal, a start of a new clock period of the second clock signal. The SoC can include a second clock divider configured to provide a second clock output signal based on the first output clock signal and the frequency indication signal.

Abstract: A package includes a first direct bonded metal (DBM) substrate, a first semiconductor die disposed on a top surface of the first DBM substrate, a second DBM substrate disposed at a height above the first DBM substrate, and a second semiconductor die disposed on a top surface of the second DBM substrate. A wire bond is made between the first semiconductor die disposed on the top surface of the first DBM substrate and the second semiconductor die disposed on the top surface of the second DBM substrate.

Abstract: A semiconductor device package may include a substrate having an insulating layer with a patterned conductive layer formed thereon, the patterned conductive layer including at least a first pattern portion and a second pattern portion. The semiconductor device package may include a leadframe having a lead that is soldered to the substrate with solder provided in an opening between the first pattern portion and the second pattern portion and with the lead inserted into the opening.

Abstract: The techniques described herein relate to a circuit including an operational amplifier that includes a differential amplifier, a capacitor, and an output stage. The differential amplifier includes a first input and a second input. The output stage is configured to generate an output voltage. The circuit includes a slew-rate boost circuitry connected to the operational amplifier. The slew-rate boost circuitry is configured to detect a voltage differential between the first input and the second input and apply, at an output of the differential amplifier, a boost current to charge the capacitor during a period of time in which the output voltage increases or decreases to a target voltage level.

Abstract: In an example, a semiconductor device includes an active trench region and an intersecting trench. The active region includes an active shield electrode and the intersecting trench includes an intersecting shield electrode. A coupling trench region connects the active trench region to the intersecting trench region. The coupling trench region includes a coupling shield electrode. The coupling shield electrode and the intersecting shield electrode are provided proximate to a termination mesa region. One or more of the coupling shield electrode or the intersecting shield electrode is thinner than the active shield electrode. The thinner shield electrode reduces depletion in the termination mesa region to improve, among other things, breakdown voltage performance.

Abstract: Implementations of methods of singulating a plurality of die included in a substrate may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a photoresist layer over the backside metal layer, patterning the photoresist layer along a die street of the substrate, and etching through the backside metal layer located in the die street of the substrate. The substrate may be exposed through the etch. The method may also include singulating the plurality of die included in the substrate through removing a substrate material in the die street.

Abstract: Various embodiments provide a filter for propagation delay compensation and interpolation in encoder digital signal processing. The filter can include a first low pass filter configured to reduce noise of a digital input comprising a measured angular position; a first differentiator configured to receive a filtered digital input and to calculate a speed from a difference in time of the measured angular position and a previous angular position; a second low pass filter configured to reduce noise from the speed; a second differentiator configured to receive a filtered speed and to calculate acceleration using a difference in time of the filtered speed and a previous speed; a third low pass filter configured to reduce noise of the acceleration; and a delay compensator configured to receive the filtered digit input, the filtered speed, and a filtered acceleration, and to calculate a propagation delay compensated digital output.

Abstract: Methods for operating an interleaved resonant power converter, and systems and apparatuses for power conversion. The method includes generating a first pair of complementary signals to drive a first stage of the interleaved resonant power converter. The method also includes generating a second pair of complementary signals to drive a second stage of the interleaved resonant power converter. The method further includes generating a current-mode control signal based on a current sense signal of the first stage. The method also includes adjusting a switching frequency of the first pair of complementary signals based on the current-mode control signal. The method further includes adjusting a switching frequency of the second pair of complementary signals to match the switching frequency of the first pair of complementary signals.

Abstract: Implementations of a semiconductor substrate may include a wafer including a first side and a second side; and a support structure coupled to the wafer at a desired location on the first side, the second side, or both the first side and the second side. The support structure may include an organic compound.

Abstract: Implementations of methods of forming a plurality of semiconductor die may include forming a damage layer beneath a surface of a die street in a semiconductor substrate, singulating the semiconductor substrate along the die street into a plurality of semiconductor die, and removing one or more particulates in the die street after singulating through applying sonic energy to the plurality of semiconductor die.

Abstract: A method, system, and integrated circuit are provided for testing a battery within a host device for abnormal conditions. The method includes charging the battery to a fully charged state, then, applying a known load to the battery and discharging the battery to a designated depth of voltage. The known load is removed from the battery, and the open circuit voltage (OCV) of the battery is monitored over time to determine an elapsed time over which the OCV recovers to a designated recovery voltage value. Based on the determined elapsed time, the method determines if the battery has a dangerous condition.

Abstract: In an example, a method of manufacturing a semiconductor device includes providing a semiconductor substrate comprising an unpolished CZ silicon substrate, a substrate upper side, and a substrate lower side opposite to the substrate upper side. The method includes first annealing the semiconductor substrate at a first temperature in an inert environment for a first time. The method includes second annealing the semiconductor substrate at a second temperature in a wet oxidation environment for a second time. The first annealing dissolves inner wall oxide in bulk region voids and the second annealing fills the voids with semiconductor interstitials. In some examples, the CZ silicon substrate is provided from a CZ ingot grown in the presence of a magnetic field and using continuous counter-doping. The method provides, among other things, a CZ silicon substrate with reduced crystal originated particle (COP) defects, reduced oxygen concentration, and reduced radial resistivity variation.

Abstract: An electronic fuse that includes a clamp circuit to enhance the protection provided by the electronic fuse. The clamp circuit can detect a short circuit condition quickly and transmit a trigger signal to a controller so that a power transistor of the electronic fuse can be turned-OFF before the current through the power transistor causes overheating or damage. The clamp circuit is a dedicated circuit for short-circuit detection that can work with other current control circuits of the electronic fuse. The clamp circuit does not increase the power consumed by the electronic fuse while not in the short circuit condition. The clamp circuit is small and fast because it can use low-voltage devices, even as high voltages are present at the input and output of the electronic fuse.

Abstract: A receiver coil of an inductive angular position sensor can have circuit features that become smaller than reasonable for high resolution measurement designs. This is especially true when multiple receiver coils are used, such as in a three-phase configuration, and when each of the multiple receiver coils is in a twisted loop configuration. The disclosed inductive angular position sensor utilizes different spatial frequencies for a rotor coil and the receiver coils. For example, the spatial frequency of the receiver coils may be kept smaller than the rotor coil. In this condition, the fundamental frequency of the angular position sensor is shifted to the least common multiple of the spatial frequencies, making the angular resolution of the inductive angular position sensor high, while the circuit features of the receiver coils are maintained at a reasonable size.

Abstract: A system such as an imaging system may include Cyclic Redundancy Check (CRC) value generation circuitry. The CRC value generation circuitry may include a data splitter that splits an input data bit stream instead multiple split data bit streams each inserted with a number of bits having a value of 0. A plurality of CRC value generators may each have a corresponding input path to receive a respective one of the split data bit streams and generate corresponding partial CRC values. A data combiner coupled to the plurality of Cyclic Redundancy Check value generators may combine the partial CRC values to generate a final CRC value. A normalizer may be coupled between each of the plurality of CRC generators and the data combiner. Two CRC value data storage structures may help the plurality of Cyclic Redundancy Check value generators and the data combiner perform the desired CRC computations.

Abstract: Implementations of semiconductor packages may include one or more die coupled over a substrate, an electrically conductive spacer coupled over the substrate, and a clip coupled over and to the one or more die and the electrically conductive spacer. The clip may electrically couple the one or more die and the electrically conductive spacer.

Abstract: Various sensors, sensor controllers, and sensing methods are suitable for use in a multi-channel ultrasonic sensor array such as those used in systems for parking assistance, blind spot monitoring, and driver assistance. One illustrative acoustic sensing method includes: driving an acoustic transducer to send acoustic bursts each including an up-chirp in a first frequency band and a down-chirp in a second frequency band; receiving echo signals responsive to the acoustic bursts from the transducer; and using the echo signals to determine a distance or time of flight from the transducer. Another acoustic sensing method includes: driving an acoustic transducer to send acoustic bursts each including a concurrent up-chirp and down-chirp; receiving echo signals responsive to the acoustic bursts from the transducer; and using the echo signals to determine a distance or time of flight from the transducer.

Abstract: A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the interposer. A second semiconductor die is disposed over a first substrate. The first semiconductor die and second semiconductor die are power semiconductor devices. The interposer is disposed over the second semiconductor die opposite the first substrate. A second substrate is disposed over the first semiconductor die opposite the interposer. The first substrate and second substrate provide heat dissipation from the first semiconductor die and second semiconductor die from opposite sides of the semiconductor device. A plurality of first and second interconnect pads is formed in a pattern over the first semiconductor die and second semiconductor die. The second interconnect pads have a different area than the first interconnect pads to aid with alignment when stacking the assembly.