Patents Assigned to Semiconductor Components Industries, L.L.C.
  • Encapsulated chip scale package having flip-chip on lead frame structure and method
    Patent number: 7439100
    Abstract: In one embodiment, an encapsulated electronic package includes a semiconductor chip having patterned solderable pads formed on a major surface. During an assembly process, the patterned solderable pads are directly affixed to conductive leads. The assembly is encapsulated using, for example, a MAP over-molding process, and then placed through a separation process to provide individual chip scale packages having flip-chip on lead frame interconnects.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: October 21, 2008
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Joseph K. Fauty, James P. Letterman, Jr., Denise Thienpont
  • DC-DC converter and method
    Patent number: 7439716
    Abstract: A DC-DC converter and method for compensating for errors in the DC-DC converter. The DC-DC converter includes an inductor coupled for receiving a source of operating voltage through a plurality of switches. The switches are controlled by a control circuit that has first and second circuit paths that are substantially parallel to each other. Each circuit path is comprised of two switched capacitor comparators that are connected in series. The circuit paths function such that during one portion of a clock period one of the circuit paths operates in an error correction mode and the other circuit path operates in a normal mode. During a different portion of the clock period the operational modes of the circuit paths switch. This allows for a calibration interval in a sampled system in which at least one circuit path is always active and responsive to the input signals in a desired manner.
    Type: Grant
    Filed: September 12, 2006
    Date of Patent: October 21, 2008
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Michael John Gay
  • Semiconductor Package Structure Having Enhanced Thermal Dissipation Characteristics
    Publication number: 20080246130
    Abstract: In an exemplary embodiment, a packaged device having enhanced thermal dissipation characteristics includes a semiconductor chip having a major current carrying or heat generating electrode. The semiconductor chip is oriented so that the major current carrying electrode faces the top of the package or away from the next level of assembly. The packaged device further includes a conductive clip for coupling the major current carrying electrode to a next level of assembly, and a heat spreader device formed on or integral with the conductive clip. A portion of the heat spreader device may be optionally exposed.
    Type: Application
    Filed: December 20, 2004
    Publication date: October 9, 2008
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, L.L.C.
    Inventors: Francis J. Carney, Michael J. Seddon, Kent L. Kime, Dluong Ngan Leong, Yeu Wen Lee
  • Soft-Start Circuit and Method Therefor
    Publication number: 20080246450
    Abstract: In one embodiment, a soft-start circuit is configured to form drive pulses that increase in width independently of the current through the power switch during a first portion of the soft-start operation period.
    Type: Application
    Filed: January 28, 2005
    Publication date: October 9, 2008
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, L.L.C.
    Inventors: Ladislav Matyas, Francois Lhermite
  • Fault control circuit and method therefor
    Patent number: 7423856
    Abstract: In one embodiment, a fault control circuit of a switching power supply controller is configured to disable an operating voltage of the switching power supply controller responsively to a fault condition and to subsequently decouple the fault control circuit from another operating voltage.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: September 9, 2008
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Ladislav Matyas
  • Schottky diode structure with enhanced breakdown voltage and method of manufacture
    Patent number: 7417265
    Abstract: In one embodiment, a Schottky diode structure comprises a Schottky barrier layer in contact with a semiconductor material through a Schottky contact opening. A conductive ring is formed adjacent the Schottky contact opening and is separated from the semiconductor material by a thin insulating layer. Another insulating layer is formed overlying the structure, and a contact opening is formed therein. The contact opening is wider than the Schottky contact opening and exposes portions of the conductive ring. A Schottky barrier metal is formed in contact with the semiconductor material through the Schottky contact opening, and is formed in further+contact with the conductive ring.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: August 26, 2008
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Antonin Rozsypal
  • Semiconductor device having trench charge compensation regions and method
    Patent number: 7411266
    Abstract: In one embodiment, a semiconductor device is formed having charge compensation trenches in proximity to channel regions of the device. The charge compensation trenches comprise at least two opposite conductivity type semiconductor layers. A channel connecting region electrically couples the channel region to one of the at least two opposite conductivity type semiconductor layers.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: August 12, 2008
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Shanghui Larry Tu, Gordon M. Grivna
  • Semiconductor package structure and method of manufacture
    Patent number: 7402895
    Abstract: In one embodiment, a semiconductor package includes a conductive slug and columnar leads in spaced relationship thereto. The columnar leads are coupled to an electronic device attached to the slug, and are exposed at least on one side of the package opposite the die attach slug. The die attach slug is further exposed to provide a package configured in a slug up orientation.
    Type: Grant
    Filed: April 14, 2006
    Date of Patent: July 22, 2008
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Shutesh Krishnan, Jatinder Kumar
  • Method for regulating an output signal and circuit therefor
    Patent number: 7400127
    Abstract: A regulator circuit and a method for compensating for sag in the output signal of the regulator circuit. A first comparator is coupled to an input of an oscillator, which oscillator outputs a clock signal and a ramp signal. In accordance with a feedback signal from the output of the regulator circuit, the clock and ramp signals of the oscillator are reset if the output signal sags to an undesirable level. The clock and ramp signals can be reset between active edges of the clock. The reset clock and ramp signals cause the regulator circuit to increase its output voltage to reduce the sag.
    Type: Grant
    Filed: May 23, 2005
    Date of Patent: July 15, 2008
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Jeremy F. Steele
  • Power factor correction circuit and method therefor
    Patent number: 7400517
    Abstract: In one embodiment, a power factor correction circuit is configured to use a stored value of a feedback signal to assist in regulating the value of an output voltage and to bypass the sample and hold circuit if the output voltage increase to an upper limit or decreases to a lower limit.
    Type: Grant
    Filed: July 3, 2006
    Date of Patent: July 15, 2008
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Terry Allinder
  • Self-aligned transistor
    Patent number: 7397070
    Abstract: In one embodiment, a transistor is formed to use two conductors to make electrical connection to one of the active regions of the transistor.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: July 8, 2008
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Gordon M. Grivna
  • Fan out buffer and method therefor
    Patent number: 7397288
    Abstract: In one embodiment, a fan out buffer has the inputs of a plurality of output followers connected to the output of a plurality of distribution gates.
    Type: Grant
    Filed: March 21, 2005
    Date of Patent: July 8, 2008
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Ira E. Baskett
  • Semiconductor package structure for vertical mount and method
    Patent number: 7397120
    Abstract: In one embodiment, a semiconductor package structure includes a plurality of upright clips having ends with mounting surfaces for vertically mounting the package to a next level of assembly. A semiconductor chip is interposed between the upright clips together with one or more spacers.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: July 8, 2008
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Stephen St. Germain, Francis J. Carney, Bruce Alan Huling
  • Semiconductor device having enhanced performance and method
    Patent number: 7397084
    Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a localized region of doping near a portion of a channel region where current exits during operation.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: July 8, 2008
    Assignees: Semiconductor Components Industries, L.L.C., HVVI Seminconductors, Inc.
    Inventors: Gary H. Loechelt, Robert B. Davies, David H. Lutz
  • Method of forming a secondary-side controller and structure therefor
    Patent number: 7385832
    Abstract: In one embodiment, a secondary-side controller is configured to detect a burst-mode of operation and responsively block or prevent sending drive pulses to a power transistor that is coupled in the secondary side.
    Type: Grant
    Filed: July 3, 2006
    Date of Patent: June 10, 2008
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Terry Allinder
  • Semiconductor structure with improved on resistance and breakdown voltage performance
    Patent number: 7381603
    Abstract: In one embodiment, a lateral FET cell is formed in a body of semiconductor material. The lateral FET cell includes a super junction structure formed in a drift region between a drain contact and a body region. The super junction structure includes a plurality of spaced apart filled trenches having doped regions of opposite or alternating conductivity types surrounding the trenches.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: June 3, 2008
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Zia Hossain, Shanghui Larry Tu
  • Semiconductor package structure and method of manufacture
    Patent number: 7382059
    Abstract: In one embodiment, a semiconductor package is formed by adding a layer of particles to desired portions of a packing substrate. The layer of particles forms a matrix of crevices that provides a micro-lock feature for mechanically locking or engaging encapsulating materials.
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: June 3, 2008
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Harold G. Anderson, Cang Ngo, Yong Li Xu, James Mohr
  • Method of forming an EPROM cell and structure therefor
    Patent number: 7365383
    Abstract: An EPROM cell includes a control gate and a control transistor. A portion of the control transistor is formed as a portion of the control gate.
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: April 29, 2008
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Gennadiy Nemtsev, Yingping Zheng, Rajesh S. Nair
  • PWM power supply controller having multiple PWM signal assertions and method therefor
    Patent number: 7345464
    Abstract: In one embodiment, a PWM power supply controller asserts a PWM control signal synchronously to a clock signal of the PWM controller and also asserts the PWM control signal asynchronously to the clock signal.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: March 18, 2008
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Jeremy F. Steele
  • Secondary side power supply controller and method therefor
    Patent number: 7345896
    Abstract: In one embodiment, a power supply controller generates a PWM control signal that is subsequently used to control a portion of current flow in a primary side of a power supply system. THE PWM control signal is coupled to a secondary of the power supply system and used to control a synchronous rectifier that is coupled within the secondary side.
    Type: Grant
    Filed: May 10, 2004
    Date of Patent: March 18, 2008
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Dhaval Dalal