Abstract: In one embodiment, a semiconductor package includes a conductive slug and columnar leads in spaced relationship thereto. The columnar leads are coupled to an electronic device attached to the slug, and are exposed at least on one side of the package opposite the die attach slug. The die attach slug is further exposed to provide a package configured in a slug up orientation.
Abstract: A regulator circuit and a method for compensating for sag in the output signal of the regulator circuit. A first comparator is coupled to an input of an oscillator, which oscillator outputs a clock signal and a ramp signal. In accordance with a feedback signal from the output of the regulator circuit, the clock and ramp signals of the oscillator are reset if the output signal sags to an undesirable level. The clock and ramp signals can be reset between active edges of the clock. The reset clock and ramp signals cause the regulator circuit to increase its output voltage to reduce the sag.
Abstract: In one embodiment, a power factor correction circuit is configured to use a stored value of a feedback signal to assist in regulating the value of an output voltage and to bypass the sample and hold circuit if the output voltage increase to an upper limit or decreases to a lower limit.
Abstract: In one embodiment, a fan out buffer has the inputs of a plurality of output followers connected to the output of a plurality of distribution gates.
Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a localized region of doping near a portion of a channel region where current exits during operation.
Type:
Grant
Filed:
April 1, 2005
Date of Patent:
July 8, 2008
Assignees:
Semiconductor Components Industries, L.L.C., HVVI Seminconductors, Inc.
Inventors:
Gary H. Loechelt, Robert B. Davies, David H. Lutz
Abstract: In one embodiment, a semiconductor package structure includes a plurality of upright clips having ends with mounting surfaces for vertically mounting the package to a next level of assembly. A semiconductor chip is interposed between the upright clips together with one or more spacers.
Abstract: In one embodiment, a transistor is formed to use two conductors to make electrical connection to one of the active regions of the transistor.
Abstract: In one embodiment, a secondary-side controller is configured to detect a burst-mode of operation and responsively block or prevent sending drive pulses to a power transistor that is coupled in the secondary side.
Abstract: In one embodiment, a semiconductor package is formed by adding a layer of particles to desired portions of a packing substrate. The layer of particles forms a matrix of crevices that provides a micro-lock feature for mechanically locking or engaging encapsulating materials.
Abstract: In one embodiment, a lateral FET cell is formed in a body of semiconductor material. The lateral FET cell includes a super junction structure formed in a drift region between a drain contact and a body region. The super junction structure includes a plurality of spaced apart filled trenches having doped regions of opposite or alternating conductivity types surrounding the trenches.
Abstract: An EPROM cell includes a control gate and a control transistor. A portion of the control transistor is formed as a portion of the control gate.
Abstract: In one embodiment, a PWM power supply controller asserts a PWM control signal synchronously to a clock signal of the PWM controller and also asserts the PWM control signal asynchronously to the clock signal.
Abstract: In one embodiment, a power supply controller generates a PWM control signal that is subsequently used to control a portion of current flow in a primary side of a power supply system. THE PWM control signal is coupled to a secondary of the power supply system and used to control a synchronous rectifier that is coupled within the secondary side.
Abstract: A spread spectrum system having a self-oscillating delay-line digital pulse width modulator and a method for mitigating electromagnetic interference. The spread spectrum system has a pseudo-random pattern generator connected to a digital-to-analog converter, which in turn is connected to a linear regulator. The linear regulator receives a reference voltage from the digital-to-analog converter and creates a frequency varying voltage that serves as an input voltage for delay elements of a delay-line based digital pulse width modulator. In response to frequency varying input signal, the delay-line based digital pulse width modulator generates a frequency varying voltage that is input to a switching network to vary its switching frequency.
Abstract: A thyristor and a method for manufacturing the thyristor that includes a gate region extending from the first major surface into a semiconductor substrate and an anode region extending from the second major surface into the semiconductor substrate. A cathode region extends into a portion of the gate region. Optionally, enhanced doped regions extend into the gate and anode regions. A mesa structure having a height HG is formed from the first major surface and a mesa structure having a height HA is formed from the second major surface. The gate region extends under the first major surface of the semiconductor substrate and it extends vertically into the semiconductor substrate a distance that is greater than height HG. The anode region extends under the second major surface of the semiconductor substrate and it extends vertically into the semiconductor substrate a distance that is greater than height HA.
Abstract: In one embodiment, an electronic device package (1) includes a leadframe (2) with a flag (3). An electronic chip (8) is attached to the flag (3) with a die attach layer (9). A trench (16) having curved sidewalls is formed in the flag (3) in proximity to the electronic chip (8) and surrounds the periphery of the chip (8). An encapsulating layer (19) covers the chip (8), portions of the flag (3), and at least a portion of the curved trench (16). The curved trench (16) reduces the spread of die attach material across the flag (3) during chip attachment, which reduces chip and package cracking problems, and improves the adhesion of encapsulating layer (19). The shape of the curved trench (16) prevents flow of die attach material into the curved trench (16), which allows the encapsulating layer (19) to adhere to the surface of the curved trench (16).
Abstract: A circuit and a method for nullifying temperature dependence of a circuit characteristic. The circuit includes a plurality of transistors configured such that they generate a gate voltage that includes a threshold voltage as a component. The gate voltage is applied to a transistor to generate a current that is proportional to a process transconductance parameter. The current is applied to a comparator having a differential pair of transistors, wherein each transistor has a process transconductance parameter. The circuit takes the ratios of the process transconductance parameter associated with the current to that of each transistor of the differential pair. By rationing the process transconductance parameters, temperature dependence is nullified or negated. The ratios can be used to set the hysteresis voltage of the comparator.
Abstract: In one embodiment, a high voltage element is formed overlying a doped semiconductor region that can be depleted during the operation of the high voltage element.
Abstract: In one embodiment, a transistor is formed to use two conductors to make electrical connection to one of the active regions of the transistor.
Abstract: In one embodiment, a power supply controller has a variable frequency oscillator that is used for controlling a PWM controller. The power supply controller varies a frequency of the variable frequency oscillator.