Patents Assigned to Semiconductor Energy Laboratory Co., Ltd.
  • Patent number: 10734529
    Abstract: A semiconductor device including an oxide semiconductor film that includes a transistor with excellent electrical characteristics is provided. It is a semiconductor device including a transistor. The transistor includes a gate electrode, a first insulating film, an oxide semiconductor film, a source electrode, a drain electrode, and a second insulating film. The source electrode and the drain electrode each include a first conductive film, a second conductive film over and in contact with the first conductive film, and a third conductive film over and in contact with the second conductive film. The second conductive film contains copper, the first conductive film and the third conductive film include a material that inhibits diffusion of copper, and an end portion of the second conductive film includes a region containing copper and silicon.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: August 4, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasutaka Nakazawa, Junichi Koezuka, Takashi Hamochi
  • Patent number: 10734413
    Abstract: A novel metal oxide is provided. The metal oxide has a plurality of energy gaps, and includes a first region having a high energy level of a conduction band minimum and a second region having an energy level of a conduction band minimum lower than that of the first region. The second region comprises more carriers than the first region. A difference between the energy level of the conduction band minimum of the first region and the energy level of the conduction band minimum of the second region is 0.2 eV or more. The energy gap of the first region is greater than or equal to 3.3 eV and less than or equal to 4.0 eV and the energy gap of the second region is greater than or equal to 2.2 eV and less than or equal to 2.9 eV.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: August 4, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Motoki Nakashima, Haruyuki Baba
  • Patent number: 10734589
    Abstract: A novel organic compound is provided. That is, a novel organic compound that is effective in improving the element characteristics and reliability is provided. The organic compound has a benzofuroquinoxaline skeleton or a benzothienoquinoxaline skeleton. The organic compound is represented by General Formula (G1). In the formula, Q represents O or S, and each of R1 to R8 independently represents any of hydrogen, a halogeno group, a substituted or unsubstituted alkyl group having 1 to 6 carbon atoms, a substituted or unsubstituted aryl group having 6 to 12 carbon atoms, and a substituted or unsubstituted heteroaryl group having 3 to 12 carbon atoms. At least one of R1 to R8 includes a substituted or unsubstituted condensed aromatic or heteroaromatic ring having 3 to 24 carbon atoms.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: August 4, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Suzuki, Tomoya Yamaguchi, Hideko Yoshizumi, Satoshi Seo, Tatsuyoshi Takahashi, Hiromitsu Kido, Satomi Watabe
  • Publication number: 20200243626
    Abstract: A flexible input/output device and an input/output device having high resistance to repeated bending are provided. The input/output device includes a first flexible substrate, a first insulating layer over the first substrate, a first transistor over the first insulating layer, a light-emitting element over and electrically connected to the first transistor and including an EL layer between first and second electrodes, a first bonding layer over the light-emitting element, a sensing element and a second transistor over the first bonding layer and electrically connected to each other, a second insulating layer over the sensing element and the second transistor, and a second flexible substrate over the second insulating layer. In the input/output device, B/A is greater than or equal to 0.7 and less than or equal to 1.7, where A is a thickness between the EL layer and the first insulating layer and B is a thickness between the EL layer and the second insulating layer.
    Type: Application
    Filed: April 10, 2020
    Publication date: July 30, 2020
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shingo EGUCHI, Shunpei YAMAZAKI
  • Publication number: 20200243514
    Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a transistor and a capacitor. The transistor includes a first conductor and a second insulator over a first insulator; a third insulator over the first conductor and the second insulator; a fourth insulator over the third insulator; a first oxide over the fourth insulator; a second oxide and a third oxide over the first oxide; a second conductor in contact with a top surface of the third insulator, a side surface of the fourth insulator, a side surface of the first oxide, a side surface of the second oxide, and a top surface of the second oxide; a third conductor in contact with the top surface of the third insulator, a side surface of the fourth insulator, a side surface of the first oxide, a side surface of the third oxide, and a top surface of the third oxide; a fourth oxide over the first oxide; a fifth insulator over the fourth oxide; and a fourth conductor over the fifth insulator.
    Type: Application
    Filed: November 26, 2019
    Publication date: July 30, 2020
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Tatsuya ONUKI, Katsuaki TOCHIBAYASHI
  • Publication number: 20200243654
    Abstract: A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle ?1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle ?2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.
    Type: Application
    Filed: April 13, 2020
    Publication date: July 30, 2020
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Daisuke Kawae
  • Publication number: 20200243569
    Abstract: The circuit includes a first transistor; a second transistor whose first terminal is connected to a gate of the first transistor for setting the potential of the gate of the first transistor to a level at which the first transistor is turned on; a third transistor for setting the potential of a gate of the second transistor to a level at which the second transistor is turned on and bringing the gate of the second transistor into a floating state; and a fourth transistor for setting the potential of the gate of the second transistor to a level at which the second transistor is turned off. With such a configuration, a potential difference between the gate and a source of the second transistor can be kept at a level higher than the threshold voltage of the second transistor, so that operation speed can be improved.
    Type: Application
    Filed: March 26, 2020
    Publication date: July 30, 2020
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi UMEZAKI
  • Patent number: 10725341
    Abstract: By increasing an interval between electrodes which drives liquid crystals, a gradient of an electric field applied between the electrodes can be controlled and an optimal electric field can be applied between the electrodes. The invention includes a first electrode formed over a substrate, an insulating film formed over the substrate and the first electrode, a thin film transistor including a semiconductor film in which a source, a channel region, and a drain are formed over the insulating film, a second electrode located over the semiconductor film and the first electrode and including first opening patterns, and liquid crystals provided over the second electrode.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: July 28, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 10725502
    Abstract: An electronic device includes a housing and a display panel. The housing includes a flat surface, a first side surface including a curved surface, second and third side surfaces adjacent to the first side surface and including a curved surface, and a fourth side surface opposite to the first side surface and including a curved surface. The display panel includes a first region overlapping with the flat surface, a second region overlapping with the first side surface and including a curved surface, a third region overlapping with the second side surface and including a curved surface, and a fourth region overlapping with the third side surface and including a curved surface.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: July 28, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiharu Hirakata, Shunpei Yamazaki
  • Patent number: 10727437
    Abstract: To realize a high-performance liquid crystal display device or light-emitting element using a plastic film. A CPU is formed over a first glass substrate and then, separated from the first substrate. A pixel portion having a light-emitting element is formed over a second glass substrate, and then, separated from the second substrate. The both are bonded to each other. Therefore, high integration can be achieved. Further, in this case, the separated layer including the CPU serves also as a sealing layer of the light-emitting element.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: July 28, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Junya Maruyama, Yumiko Ohno
  • Patent number: 10727465
    Abstract: To provide a novel structure of a separator in a secondary battery. A nonaqueous secondary battery includes a positive electrode, a negative electrode, an electrolyte solution, a first separator, and a second separator. The first separator and the second separator are provided between the positive electrode and the negative electrode. The first separator is provided with a first pore, the second separator is provided with a second pore, and the size of the first pore is different from the size of the second pore. Furthermore, the proportion of the volume of the first pores in the first separator is different from the proportion of the volume of the second pores in the second separator.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: July 28, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10726913
    Abstract: Disclosed is a semiconductor device having a memory cell which comprises a transistor having a control gate and a storage gate. The storage gate comprises an oxide semiconductor and is able to be a conductor and an insulator depending on the potential of the storage gate and the potential of the control gate. Data is written by setting the potential of the control gate to allow the storage gate to be a conductor, supplying a potential of data to be stored to the storage gate, and setting the potential of the control gate to allow the storage gate to be an insulator. Data is read by supplying a potential for reading to a read signal line connected to one of a source and a drain of the transistor and detecting the change in potential of a bit line connected to the other of the source and the drain.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: July 28, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideki Uochi, Koichiro Kamata
  • Patent number: 10727355
    Abstract: A semiconductor device includes first and second insulators over a substrate, a semiconductor over the second insulator, first and second conductors over the semiconductor, a third insulator over the semiconductor, a fourth insulator over the third insulator, a third conductor over the fourth insulator, and a fifth insulator over the first insulator, the first conductor and the second conductor. The semiconductor includes first, second, and third regions. The first region overlaps with the third conductor with the third insulator and the fourth insulator positioned therebetween. The second region overlaps with the third conductor with the first conductor, the fourth insulator, and the fifth insulator positioned therebetween. The third region overlaps with the third conductor with the second conductor, the fourth insulator, and the fifth insulator positioned therebetween. The fourth insulator is in contact with a side surface of the fifth insulator in a region overlapping with the semiconductor.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: July 28, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10727356
    Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first insulator over a substrate; a first oxide over the first insulator; a second oxide in contact with at least a portion of the top surface of the first oxide; a second insulator over the second oxide; a first conductor over the second insulator; a second conductor over the first conductor; a third insulator over the second conductor; a fourth insulator in contact with side surfaces of the second insulator, the first conductor, the second conductor, and the third insulator; and a fifth insulator in contact with the top surface of the second oxide and a side surface of the fourth insulator. The top surface of the fourth insulator is substantially aligned with the top surface of the third insulator.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: July 28, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Publication number: 20200234108
    Abstract: To provide a semiconductor device which can execute the product-sum operation. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. First analog data is stored in the first memory cell, and reference analog data is stored in the second memory cell. The first memory cell and the second memory cell supply a first current and a second current, respectively, when a reference potential is applied as a selection signal. The offset circuit has a function of supplying a third current corresponding to a differential current between the first current and the second current. In the semiconductor device, the first memory and the second memory supply a fourth current and a fifth current, respectively, when a potential corresponding to second analog data is applied as a selection signal.
    Type: Application
    Filed: March 23, 2020
    Publication date: July 23, 2020
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Yoshiyuki KUROKAWA
  • Publication number: 20200233509
    Abstract: To provide a thin touch panel, a touch panel with high visibility, a lightweight touch panel, or a touch panel with low power consumption. A pair of conductive layers included in a capacitive touch sensor have a mesh shape including a plurality of openings. Furthermore, a material blocking visible light is provided to overlap with a region between two display elements in a plan view; thus, a light-blocking layer can be obtained. Furthermore, the pair of conductive layers included in the touch sensor are provided between a pair of substrates included in the touch panel, and a conductive layer capable of supplying a constant potential is provided between a circuit which drives a display element and the pair of conductive layers.
    Type: Application
    Filed: February 11, 2020
    Publication date: July 23, 2020
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideaki Shishido, Yoshiharu Hirakata, Daisuke Kubota
  • Publication number: 20200235100
    Abstract: A semiconductor device having high frequency characteristics and high reliability is provided. Part of metal elements included in the oxide semiconductor including indium is replaced with cerium (Ce). When indium (In) included in the oxide semiconductor is replaced with cerium, electrons serving as carriers are released. Thus, by adjusting the ratio of cerium included in the oxide semiconductor, the carrier density of the oxide semiconductor can be controlled. In the case where the transistor is used for a memory element or the like, a cerium atom may be greater than or equal to 0.01 atomic % and less than or equal to 1.0 atomic % of metal atoms included in the oxide semiconductor.
    Type: Application
    Filed: November 15, 2018
    Publication date: July 23, 2020
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei YAMAZAKI, Tomonori NAKAYAMA, Haruyuki BABA
  • Patent number: 10720433
    Abstract: The semiconductor device includes: a transistor having an oxide semiconductor layer; and a logic circuit formed using a semiconductor material other than an oxide semiconductor. One of a source electrode and a drain electrode of the transistor is electrically connected to at least one input of the logic circuit, and at least one input signal is applied to the logic circuit through the transistor. The off-current of the transistor is preferably 1×10?13 A or less.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: July 21, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Keitaro Imai, Jun Koyama
  • Patent number: 10720452
    Abstract: To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: July 21, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Umezaki
  • Patent number: 10720532
    Abstract: A semiconductor device having a structure which can prevent a decrease in electrical characteristics due to miniaturization is provided. The semiconductor device includes, over an insulating surface, a stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed, and a third oxide semiconductor layer covering part of a surface of the stack. The third oxide semiconductor layer includes a first layer in contact with the stack and a second layer over the first layer. The first layer includes a microcrystalline layer, and the second layer includes a crystalline layer in which c-axes are aligned in a direction perpendicular to a surface of the first layer.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: July 21, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masayuki Sakakura, Hideomi Suzawa