Patents Assigned to Semiconductor Energy Laboratory Co., Ltd.
  • Patent number: 12040653
    Abstract: The safety is ensured in such a manner that with an abnormality detection system of a secondary battery, abnormality of a secondary battery is detected, for example, a phenomenon that lowers the safety of the secondary battery is detected early, and a user is warned or the use of the secondary battery is stopped. The abnormality detection system of the secondary battery determines whether the temperature of the secondary battery is within a temperature range in which normal operation can be performed on the basis of temperature data obtained with a temperature sensor. In the case where the temperature of the secondary battery is high, a cooling device is driven by a control signal from the abnormality detection system of the secondary battery. The abnormality detection system of the secondary battery includes at least a memory means. The memory means has a function of holding an analog signal and includes a transistor using an oxide semiconductor for a semiconductor layer.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: July 16, 2024
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Munehiro Kozuma, Takayuki Ikeda, Takanori Matsuzaki, Kei Takahashi, Mayumi Mikami, Shunpei Yamazaki
  • Patent number: 12041762
    Abstract: A semiconductor device in which temperature dependence is reduced is provided. A switched capacitor is formed using a second transistor, a third transistor, and a second capacitor. Semiconductor layers of the second transistor and the third transistor that include an oxide can reduce temperature dependence. An AC signal supplied to the gates of the second transistor and the third transistor is converted into a DC voltage through the switched capacitor. Note that the level of the DC voltage is adjusted by the levels of the voltages supplied to the back gates of the second transistor and the third transistor.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: July 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuaki Ohshima, Hitoshi Kunitake, Takahiro Fukutome
  • Patent number: 12041800
    Abstract: An imaging device having a color imaging function and an infrared imaging function is provided. The imaging device has a structure in which a first photoelectric conversion device and a second photoelectric conversion device are stacked, and the second photoelectric conversion device generates electric charge by absorbing infrared light and transmits light having a wavelength of a higher energy than that of infrared light. The first photoelectric conversion device is positioned to overlap with the second photoelectric conversion device, and generates electric charge by absorbing light (visible light) passing through the second photoelectric conversion device. Thus, a subpixel for color imaging and a subpixel for infrared imaging can be positioned to overlap with each other, and an infrared imaging function can be added without a decrease in the definition of color imaging.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: July 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takuro Kanemura, Yusuke Negoro
  • Patent number: 12040042
    Abstract: An object of one embodiment of the present invention is to propose a memory device in which a period in which data is held is ensured and memory capacity per unit area can be increased. In the memory device of one embodiment of the present invention, bit lines are divided into groups, and word lines are also divided into groups. The word lines assigned to one group are connected to the memory cell connected to the bit lines assigned to the one group. Further, the driving of each group of bit lines is controlled by a dedicated bit line driver circuit of a plurality of bit line driver circuits. In addition, cell arrays are formed on a driver circuit including the above plurality of bit line driver circuits and a word line driver circuit. The driver circuit and the cell arrays overlap each other.
    Type: Grant
    Filed: January 25, 2023
    Date of Patent: July 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Shunpei Yamazaki
  • Patent number: 12040795
    Abstract: A semiconductor device using unipolar transistors, in which high and low levels are expressed using high and low power supply potentials, is provided. The semiconductor device includes four transistors, two capacitors, two wirings, two input terminals, and an output terminal. A source or a drain of the first transistor and a source or a drain of the fourth transistor are electrically connected to the first wiring. A gate of the fourth transistor is electrically connected to the first input terminal, and a gate of the second transistor is electrically connected to the second input terminal. A source or a drain of the second transistor and a source or a drain of the third transistor are electrically connected to the second wiring. The first transistor, the second transistor, and the two capacitors are electrically connected to the output terminal.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: July 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Inoue, Munehiro Kozuma, Takeshi Aoki, Shuji Fukai, Fumika Akasawa, Shintaro Harada, Sho Nagao
  • Patent number: 12039952
    Abstract: A display apparatus which includes a driver with low power consumption and in which an output voltage of the driver is boosted by a pixel is provided. The source driver in which a logic unit and an amplifier unit operate appropriately by the same low voltage is included, and the pixel has a function of retaining first data, a function of adding second data to the first data to generate third data, and a function of supplying the third data to a display device. Thus, even when a voltage output from the source driver is low, the voltage can be boosted by the pixel; accordingly, the display device can operate appropriately.
    Type: Grant
    Filed: April 13, 2023
    Date of Patent: July 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kouhei Toyotaka, Motoharu Saito
  • Patent number: 12041366
    Abstract: An imaging device having a function of processing an image is provided. The imaging device has an additional function such as image processing, can hold analog data obtained by an image capturing operation in a pixel, and can extract data obtained by multiplying the analog data by a predetermined weight coefficient. Difference data between adjacent light-receiving devices can be obtained in a pixel, and data on luminance gradient can be obtained. When the data is taken in a neural network or the like, inference of distance data or the like can be performed. Since enormous volume of image data in the state of analog data can be held in pixels, processing can be performed efficiently.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: July 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeya Hirose, Seiichi Yoneda, Hiroki Inoue, Takayuki Ikeda, Shunpei Yamazaki
  • Patent number: 12040007
    Abstract: A semiconductor device with reduced power consumption is provided. The semiconductor device includes a transmitter unit, a receiver unit, a bias-outputting unit, and a controller unit. The bias-outputting unit has a plurality of memory units. The plurality of memory units each retains information to determine transmission power. The receiver unit receives a request signal transmitted from a base station and supplies it to the controller unit. The controller unit selects one of the plurality of memory units according to the request signal. The memory unit has an OS transistor and retains information when power supply is stopped.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: July 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Munehiro Kozuma, Takayuki Ikeda, Kei Takahashi, Takeshi Aoki
  • Patent number: 12041765
    Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a transistor and a capacitor. The transistor includes a metal oxide and a first conductor that is electrically connected to the metal oxide. The capacitor includes a first insulator which is provided over the metal oxide and which the first conductor penetrates; a second insulator provided over the first insulator and including an opening reaching the first insulator and the first conductor; a second conductor in contact with an inner wall of the opening, the first insulator, and the first conductor; a third insulator provided over the second conductor; and a fourth conductor provided over the third insulator. The first insulator has higher capability of inhibiting the passage of hydrogen than the second insulator.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: July 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuichi Sato, Ryota Hodo, Yuta Iida, Tomoaki Moriwaka
  • Patent number: 12040009
    Abstract: A sense amplifier and a semiconductor device which are less likely to be influenced by a variation in transistor characteristics and their operation methods are provided. An amplifier circuit in a sense amplifier includes a first circuit and a second circuit, each including an inverter, a first transistor, a second transistor, and a capacitor. A first terminal and a second terminal of the capacitor are electrically connected to a first bit line and an input terminal of the inverter, respectively. The first transistor and the second transistor function as a switch that switches conduction and non-conduction between the input terminal and an output terminal of the inverter, and a switch that switches conduction and non-conduction between the output terminal of the inverter and the second bit line, respectively. The first circuit and the second circuit are initialized by a potential obtained when conduction is established between the input terminal and the output terminal of the inverter.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: July 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hajime Kimura
  • Publication number: 20240237435
    Abstract: A semiconductor device with reduced circuit area is provided. The semiconductor device includes first and second cell arrays and a first converter circuit. The first cell array includes a first cell and a second cell in the same row, and the second cell array includes third and fourth cells in the same row. The first cell is electrically connected to first and second wirings, the second cell is electrically connected to the first and third wirings, the third cell is electrically connected to fourth and sixth wirings, and the fourth cell is electrically connected to fifth and seventh wirings. The sixth wiring is electrically connected to the seventh wiring. The first to fourth cells each have a function of outputting current corresponding to a product of retained data and input data. Specifically, the first cell, the second cell, the third cell, and the fourth cell output current to the second wiring, the third wiring, the sixth wiring, and the seventh wiring, respectively.
    Type: Application
    Filed: April 20, 2022
    Publication date: July 11, 2024
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuki TSUDA, Hidefumi RIKIMARU, Satoru OHSHITA, Hiromichi GODO, Yoshiyuki KUROKAWA
  • Publication number: 20240234578
    Abstract: A semiconductor device with favorable electrical characteristics is provided. A semiconductor device with stable electrical characteristics is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, and a first conductive layer. The first insulating layer is provided over the semiconductor layer. The first conductive layer is provided over the first insulating layer. The semiconductor layer includes a first region that overlaps with the first conductive layer and the first insulating layer, a second region that does not overlap with the first conductive layer and overlaps with the first insulating layer, and a third region that overlaps with neither the first conductive layer nor the first insulating layer. The semiconductor layer contains a metal oxide. The second region and the third region contain a first element. The first element is one or more elements selected from boron, phosphorus, aluminum, and magnesium.
    Type: Application
    Filed: October 11, 2023
    Publication date: July 11, 2024
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kenichi OKAZAKI, Masami JINTYOU, Kensuke YOSHIZUMI
  • Publication number: 20240237414
    Abstract: A display apparatus having an image capturing function is provided. A display apparatus or an image capturing device with a high aperture ratio is provided. The display apparatus includes a first light-emitting element and a light-receiving element. The first light-emitting element includes a first pixel electrode, a first organic layer, and a common electrode. The light-receiving element includes a second pixel electrode, a second organic layer, and the common electrode. The first organic layer includes a first light-emitting layer, and the second organic layer includes a photoelectric conversion layer. A first layer and a second layer are included in a region between the first light-emitting element and the light-receiving element. The first layer overlaps with the second organic layer and the second pixel electrode and contains a material identical to a material of the first organic layer.
    Type: Application
    Filed: April 29, 2022
    Publication date: July 11, 2024
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daisuke Kubota, Kenichi OKAZAKI, Ryo HATSUMI, Koji KUSUNOKI
  • Publication number: 20240234423
    Abstract: Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.
    Type: Application
    Filed: December 13, 2023
    Publication date: July 11, 2024
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Shunpei YAMAZAKI
  • Publication number: 20240233677
    Abstract: To provide a semiconductor device including a narrowed bezel obtained by designing a gate driver circuit. A gate driver of a display device includes a shift register unit, a demultiplexer circuit, and n signal lines. By connecting the n signal lines for transmitting clock signals to one stage of the shift register unit, (n?3) output signals can be output. The larger n becomes, the smaller the rate of signal lines for transmitting clock signals which do not contribute to output becomes; accordingly, the area of the shift register unit part is small compared to a conventional structure in which one stage of a shift register unit outputs one output signal. Therefore, the gate driver circuit can have a narrow bezel.
    Type: Application
    Filed: January 4, 2024
    Publication date: July 11, 2024
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroyuki Miyake, Kouhei Toyotaka, Shunpei Yamazaki
  • Patent number: 12034080
    Abstract: To suppress a change in electrical characteristics in a transistor including an oxide semiconductor film. The transistor includes a first gate electrode, a first insulating film, an oxide semiconductor film, a source electrode, a drain electrode, a second insulating film, a second gate electrode, and a third insulating film. The oxide semiconductor film includes a first oxide semiconductor film on the first gate electrode side, and a second oxide semiconductor film over the first oxide semiconductor film. The first oxide semiconductor film and the second oxide semiconductor film include In, M, and Zn (M is Al, Ga, Y, or Sn). In a region of the second oxide semiconductor film, the number of atoms of In is smaller than that in the first oxide semiconductor film. The second gate electrode includes at least one metal element included in the oxide semiconductor film.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: July 9, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Kenichi Okazaki, Yasuharu Hosaka, Masami Jintyou, Takahiro Iguchi, Shunpei Yamazaki
  • Patent number: 12034327
    Abstract: Deterioration of a power storage device is reduced. Switches that control the connections of a plurality of power storage devices separately are provided. The switches are controlled with a plurality of control signals, so as to switch between charge and discharge of each of the power storage devices or between serial connection and parallel connection of the plurality of power storage devices. Further, a semiconductor circuit having a function of carrying out arithmetic is provided for the power storage devices, so that a control system of the power storage devices or a power storage system is constructed.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: July 9, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Minoru Takahashi, Junpei Momo, Yutaka Shionoiri
  • Patent number: 12033867
    Abstract: In a transistor including an oxide semiconductor layer, an oxide insulating layer is formed so as to be in contact with the oxide semiconductor layer. Then, oxygen is introduced (added) to the oxide semiconductor layer through the oxide insulating layer, and heat treatment is performed. Through these steps of oxygen introduction and heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor layer, so that the oxide semiconductor layer is highly purified.
    Type: Grant
    Filed: May 2, 2023
    Date of Patent: July 9, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka
  • Patent number: 12034322
    Abstract: A battery control circuit having a novel structure, a battery protection circuit having a novel structure, and a power storage device including the battery circuit are provided. A semiconductor device includes n cell balancing circuits that respectively correspond to one secondary battery and each include a transistor, a comparator circuit, and a capacitor. In each of the n cell balancing circuits, an inverting input terminal of the comparator circuit and one electrode of the capacitor are electrically connected to one of a source and a drain of the transistor.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: July 9, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuki Okamoto, Takahiko Ishizu, Kei Takahashi, Takayuki Ikeda
  • Patent number: 12035061
    Abstract: An imaging device having a memory function is provided. Alternatively, an imaging device suitable for taking images of a moving object is provided. The imaging device includes a first to third layers; the second layer is provided between the first and the third layer; the first layer includes a photoelectric conversion device; the second layer includes a first and a second circuit; the third layer includes a third and a fourth circuit; the first circuit and the photoelectric conversion device have a function of generating imaging data; the third circuit has a function of reading the imaging data; the second circuit has a function of storing the imaging data read by the third circuit; the fourth circuit has a function of reading the imaging data stored in the second circuit; and the first circuit and the second circuit include a transistor including a metal oxide in a channel formation region.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: July 9, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takayuki Ikeda