Patents Assigned to Semiconductor Energy Laboratory Co., Ltd.
  • Publication number: 20210225942
    Abstract: A novel display panel that is highly convenient or reliable is provided. The display panel includes a first pixel; the first pixel includes a first display element, a first color conversion layer, and a first absorption layer; the first display element emits first light; the first absorption layer overlaps with the first display element; and the first absorption layer absorbs the first light. Furthermore, the first color conversion layer is sandwiched between the first display element and the first absorption layer; the first color conversion layer converts the first light into second light; and the second light has a spectrum including a high proportion of light with a long wavelength compared with the first light.
    Type: Application
    Filed: May 29, 2019
    Publication date: July 22, 2021
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tsunenori SUZUKI, Yasuhiro NIIKURA, Tomoya HIROSE, Satoshi SEO
  • Publication number: 20210226146
    Abstract: A light-emitting element having high external quantum efficiency is provided. A light-emitting element having low drive voltage is provided. Provided is a light-emitting element which includes a light-emitting layer containing a phosphorescent compound, a first organic compound, and a second organic compound between a pair of electrodes. A combination of the first organic compound and the second organic compound forms an exciplex (excited complex). An emission spectrum of the exciplex overlaps with an absorption band located on the longest wavelength side of an absorption spectrum of the phosphorescent compound. A peak wavelength of the emission spectrum of the exciplex is longer than or equal to a peak wavelength of the absorption band located on the longest wavelength side of the absorption spectrum of the phosphorescent compound.
    Type: Application
    Filed: April 5, 2021
    Publication date: July 22, 2021
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Satoshi Seo, Satoko Shitagaki, Nobuharu Ohsawa, Hideko Inoue, Kunihiko Suzuki
  • Publication number: 20210226060
    Abstract: A transistor including an oxide semiconductor layer can have stable electrical characteristics. In addition, a highly reliable semiconductor device including the transistor is provided. A semiconductor device includes a multi-layer film including an oxide layer and an oxide semiconductor layer, a gate insulating film in contact with the multi-layer film, and a gate electrode overlapping with the multi-layer film with the gate insulating film provided therebetween. In the semiconductor device, the oxide semiconductor layer contains indium, the oxide semiconductor layer is in contact with the oxide layer, and the oxide layer contains indium and has a larger energy gap than the oxide semiconductor layer.
    Type: Application
    Filed: February 23, 2021
    Publication date: July 22, 2021
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Shunpei Yamazaki
  • Patent number: 11066739
    Abstract: There have been cases where transistors formed using oxide semiconductors are inferior in reliability to transistors formed using amorphous silicon. Thus, in the present invention, a semiconductor device including a highly reliable transistor formed using an oxide semiconductor is manufactured. An oxide semiconductor film is deposited by a sputtering method, using a sputtering target including an oxide semiconductor having crystallinity, and in which the direction of the c-axis of a crystal is parallel to a normal vector of the top surface of the oxide semiconductor. The target is formed by mixing raw materials so that its composition ratio can obtain a crystal structure.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: July 20, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Tetsunori Maruyama, Yuki Imoto, Hitomi Sato, Masahiro Watanabe, Mitsuo Mashiyama, Kenichi Okazaki, Motoki Nakashima, Takashi Shimazu
  • Patent number: 11071224
    Abstract: A novel, highly convenient or reliable functional panel is provided. A novel, highly convenient or reliable method for manufacturing a functional panel is provided. The functional panel includes a first base; a second base having a region overlapping with the first base; a bonding layer that bonds the first base to the second base; and an insulating layer in contact with the first base, the second base, and the bonding layer. With this structure, an opening which is formed easily in a region where the bonding layer is in contact with the first base or the second base can be filled with the insulating layer, which can prevent impurities from being diffused into the functional layer located in a region surrounded by the first base, the second base, and the bonding layer that bonds the first base to the second base.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: July 20, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kohei Yokoyama, Yoshiharu Hirakata
  • Patent number: 11068174
    Abstract: Power consumption of an interface circuit is to be reduced. A semiconductor device includes a processor and the interface circuit including a register that stores setting information. The register includes a first memory circuit capable of storing the setting information when power supply voltage is supplied, and a second memory capable of storing the setting information when supply of the power supply voltage is stopped. The interface circuit changes a state between a first state, a second state, a third state, and a fourth state. In the first state, the setting information is stored in the first memory. In the second state, the interface circuit operates on the basis of the setting information stored in the first memory circuit. In the third state, the setting information stored in the first memory circuit is stored in the second memory circuit and the supply of the power supply voltage is stopped.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: July 20, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 11067841
    Abstract: Provided is a display device having high visibility regardless of the intensity of external light. Provided is a display device capable of a variety of display. Provided is a display device that can operate with low power consumption. The display device includes a first electrode, a second electrode, a first liquid crystal layer, a second liquid crystal layer, a first coloring layer, and a first insulating layer. The first liquid crystal layer overlaps with the second liquid crystal layer with the first insulating layer therebetween. The first electrode is configured to reflect visible light. The second electrode includes a portion not overlapping with the first electrode and is configured to transmit visible light. The second liquid crystal layer includes a first portion overlapping with the first coloring layer and the second electrode, and a second portion not overlapping with the first coloring layer. The first portion contains monomers and liquid crystal.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: July 20, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daisuke Kubota, Masaru Nakano
  • Patent number: 11069747
    Abstract: To provide a display device that is suitable for increasing in size, a display device in which display unevenness is suppressed, or a display device that can display an image along a curved surface. The display device includes a first display panel and a second display panel each including a pair of substrates. The first display panel and the second display panel each include a first region which can transmit visible light, a second region which can block visible light, and a third region which can perform display. The third region of the first display panel and the first region of the second display panel overlap each other. The third region of the first display panel and the second region of the second display panel do not overlap each other.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: July 20, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroyuki Miyake, Hisao Ikeda
  • Patent number: 11069718
    Abstract: A novel display device or the like in which a transistor connected to a scan line has small gate capacitance is provided. A novel display device or the like in which a scan line has low resistance is provided. A novel display device or the like in which pixels can be arranged with high density is provided. A novel display device or the like that can be manufactured without an increase in cost is provided. In a transistor including a first gate electrode and a second gate electrode, the first gate electrode is formed using a metal material with low resistance and the second gate electrode is formed using a metal oxide material that can reduce oxygen vacancies in an oxide semiconductor layer. The first gate electrode is connected to the scan line, and the second gate electrode is connected to a wiring to which a constant potential is supplied.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: July 20, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kouhei Toyotaka, Kei Takahashi, Hideaki Shishido, Koji Kusunoki
  • Patent number: 11069796
    Abstract: A semiconductor layer containing a metal oxide is formed, a gate insulating layer containing an oxide is formed over the semiconductor layer, and a metal oxide layer is formed over the gate insulating layer. Heat treatment is performed after the metal oxide layer is formed, and the metal oxide layer is removed after the heat treatment is performed. After the metal oxide layer is removed, a gate electrode overlapping with part of the semiconductor layer is formed over the gate insulating layer. Then, a first element is supplied through the gate insulating layer to a region of the semiconductor layer that does not overlap with the gate electrode. Examples of the first element include phosphorus, boron, magnesium, aluminum, and silicon. The steps performed after the metal oxide layer is removed are each preferably performed at a temperature lower than or equal to the temperature of the heat treatment.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: July 20, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Kenichi Okazaki, Masataka Nakada, Yasuharu Hosaka
  • Patent number: 11069717
    Abstract: To provide a novel material. In a field-effect transistor including a metal oxide, a channel formation region of the transistor includes a material having at least two different energy band widths. The material includes nano-size particles each with a size of greater than or equal to 0.5 nm and less than or equal to 10 nm. The nano-size particles are dispersed or distributed in a mosaic pattern.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: July 20, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 11069816
    Abstract: A semiconductor device that can be highly integrated is provided. The semiconductor device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a first conductive layer, and a second conductive layer. The second semiconductor layer is positioned over the first semiconductor layer, the second conductive layer is positioned on the second semiconductor layer, and the second insulating layer is provided so as to cover a top surface and a side surface of the second conductive layer. The second conductive layer and the second insulating layer include a first opening, and the third semiconductor layer is provided in contact with a top surface of the second insulating layer, a side surface of the first opening, and the second semiconductor layer.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: July 20, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yukinori Shima, Masataka Nakada, Masayoshi Dobashi, Kenichi Okazaki
  • Patent number: 11069817
    Abstract: A display device including a pixel having a memory. The pixel includes at least a display element, a capacitor, an inverter, and a switch. The switch is controlled with a signal held in the capacitor and a signal output from the inverter so that voltage is supplied to the display element. The inverter and the switch can be constituted by transistors with the same polarity. A semiconductor layer included in the pixel may be formed using a light-transmitting material. Moreover, a gate electrode, a drain electrode, and a capacitor electrode may be formed using a light-transmitting conductive layer. The pixel is formed using a light-transmitting material in such a manner, whereby the display device can be a transmissive display device while including a pixel having a memory.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: July 20, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Kengo Akimoto, Masashi Tsubuku, Toshinari Sasaki
  • Publication number: 20210214381
    Abstract: Providing a novel organometallic complex represented by Structure Formula (G1). A1 to A4 independently represent an alkyl group having 1 to 6 carbon atoms or a cycloalkyl group having 3 to 6 carbon atoms. R1 to R5 independently represent any one of hydrogen, an alkyl group having 1 to 6 carbon atoms, a cycloalkyl group having 3 to 6 carbon atoms, and a cyano group, wherein at least one of R1 to R5 represents a cyano group. R11 to R14 independently represent an alkyl group having 2 to 6 carbon atoms or a cycloalkyl group having 3 to 6 carbon atoms. R15 and R16 independently represent any one of hydrogen, a methyl group, and an ethyl group. Note that R11 and R12 may be bonded to each other to form a ring, and R13 and R14 may be bonded to each other to form a ring.
    Type: Application
    Filed: December 30, 2020
    Publication date: July 15, 2021
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Tomoya YAMAGUCHI, Hideko YOSHIZUMI, Yuta KAWANO, Takeyoshi WATABE, Satoshi SEO
  • Publication number: 20210217805
    Abstract: A display device with high resolution is provided. Manufacturing cost of a display device using a micro LED as a display element is reduced. The display device includes a substrate, a plurality of transistors, and a plurality of light-emitting diodes. The plurality of light-emitting diodes are provided in a matrix over the substrate. Each of the plurality of transistors are electrically connected to at least one of the plurality of light-emitting diodes. The plurality of light-emitting diodes are positioned closer to the substrate than the plurality of transistors are. The plurality of light-emitting diodes emit light to the opposite side of the substrate.
    Type: Application
    Filed: April 26, 2019
    Publication date: July 15, 2021
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Koji KUSUNOKI, Shingo EGUCHI, Yosuke TSUKAMOTO, Kazunori WATANABE, Kouhei TOYOTAKA
  • Publication number: 20210217898
    Abstract: It is an object of the present invention to connect a wiring, an electrode, or the like formed with two incompatible films (an ITO film and an aluminum film) without increasing the cross-sectional area of the wiring and to achieve lower power consumption even when the screen size becomes larger. The present invention provides a two-layer structure including an upper layer and a lower layer having a larger width than the upper layer. A first conductive layer is formed with Ti or Mo, and a second conductive layer is formed with aluminum (pure aluminum) having low electric resistance over the first conductive layer. A part of the lower layer projected from the end section of the upper layer is bonded with ITO.
    Type: Application
    Filed: January 21, 2021
    Publication date: July 15, 2021
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshinari Higaki, Masayuki SAKAKURA, Shunpei YAMAZAKI
  • Patent number: 11063236
    Abstract: There has been a problem that difference in refractive index between an opposite substrate or a moisture barrier layer provided thereover, and air is maintained large, and light extraction efficiency is low. Further, there has been a problem that peeling or cracking due to the moisture barrier layer is easily generated, which leads to deteriorate the reliability and lifetime of a light-emitting element. A light-emitting element comprises a pixel electrode, an electroluminescent layer, a transparent electrode, a passivation film, a stress relieving layer, and a low refractive index layer, all of which are stacked sequentially. The stress relieving layer serves to prevent peeling of the passivation film. The low refractive index layer serves to reduce reflectivity of light generated in the electroluminescent layer in emitting to air. Therefore, a light-emitting element with high reliability and long lifetime and a display device using the light-emitting element can be provided.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: July 13, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisao Ikeda, Hiroki Ohara, Makoto Hosoba, Junichiro Sakata, Shunichi Ito
  • Patent number: 11062762
    Abstract: A data reading error is reduced. A memory cell array in a storage device includes a write word line, a read word line, a write bit line, a read bit line, a source line, and a gain cell. For example, a read transistor in the gain cell can include a metal oxide in a channel formation region. A cancel circuit is electrically connected to the read bit line. The cancel circuit has a function of supplying, to the read bit line, current for canceling leakage current supplied to the read bit line from the gain cell in a non-selected state. In read operation, a potential change of the read bit line due to leakage current is compensated for by the current from the cancel circuit, so that a data reading error is reduced.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: July 13, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takahiko Ishizu, Shuhei Nagatsuka
  • Patent number: 11063047
    Abstract: A semiconductor device with a large storage capacity per unit area is provided. The disclosed semiconductor device includes a plurality of gain-cell memory cells each stacked over a substrate. Axes of channel length directions of write transistors of memory cells correspond to each other, and are substantially perpendicular to the top surface of the substrate. The semiconductor device can retain multi-level data. The channel of read transistors is columnar silicon (embedded in a hole penetrating gates of the read transistors). The channel of write transistors is columnar metal oxide (embedded in a hole penetrating the gates of the read transistors and gates, or write word lines, of the write transistors). The columnar silicon faces the gate of the read transistor with an insulating film therebetween. The columnar metal oxide faces the write word line with an insulating film, which is obtained by oxidizing the write word line, therebetween, and is electrically connected to the gate of the read transistor.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: July 13, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuhiko Takemura, Yoshiyuki Kurokawa
  • Patent number: 11061285
    Abstract: By increasing an interval between electrodes which drives liquid crystals, a gradient of an electric field applied between the electrodes can be controlled and an optimal electric field can be applied between the electrodes. The invention includes a first electrode formed over a substrate, an insulating film formed over the substrate and the first electrode, a thin film transistor including a semiconductor film in which a source, a channel region, and a drain are formed over the insulating film, a second electrode located over the semiconductor film and the first electrode and including first opening patterns, and liquid crystals provided over the second electrode.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: July 13, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura