Abstract: A heat treatment is performed to an insulating film composition, formed on a semiconductor substrates at a temperature of 350° C. in an inert gas ambient to form a non-porous insulating film. Next, dry etching is performed using a resist pattern as a mask to form a trench in the non-porous insulating film, ashing is performed to remove the resist pattern, and the surface of the semiconductor substrate is cleaned. Thereafter, a second heat treatment is performed for the non-porous insulating film to form a porous insulating film. Since the second heat treatment is performed in an oxidizing-gas atmosphere, the pore-generating material can be removed at a temperature lower than the temperature of conventional methods to form an insulating film having a low dielectric constant.

Abstract: A first insulating film, a second insulating film, a third insulating film, an antireflective film, and a resist film are formed in this order on a lower-layer wiring. After dry etching the third insulating film and the second insulating film, using the resist film as a mask, the resist film and the antireflective film are removed by ashing. Thereafter, the first insulating film is dry etched, using the third insulating film as a mask, to form a wiring trench extending to the lower-layer wiring. The dry etching of the third insulating film and the second insulating film is performed using a gas containing fluorine at a pressure of 0.1 Pa to 4 Pa. Ashing is preferably performed using at least one of hydrogen and an inert gas.

Abstract: An ion implantation simulator that computes an ion density distribution at high speed and with high accuracy based on a beam dispersion phenomenon in an ion implantation process. The ion implantation simulator is provided with the beam dispersion approximate function storage section 121, which stores a beam dispersion approximate function that is obtained through approximation of ion beam dispersion by using a predetermined function; a beam intensity computing section 131, which computes an area surface beam intensity that indicates an intensity of the ion beam on a surface of an implanted area by using the beam dispersion approximate function; and an ion density distribution computing section 132, which computes the density distribution of the ion, which is implanted by the ion beam into the device through the surface of the implanted area, by using the area surface beam intensity.

Abstract: A semiconductor device having a first wiring layer including first wirings on a substrate, a contact layer on the first wiring layer and including contacts connected to the first wirings, and a second wiring layer on the contact layer and including second wirings connected to the contacts. Contact pitch is larger than the minimum wiring pitch of the first wirings or the minimum wiring pitch of the second wirings.

Abstract: A method of forming an inorganic porous film comprises applying, to a support, an inorganic material composition including a mixture of a silicon oxide precursor containing at least one hydrolyzable silane compound and a pore-generating material, thereby forming a film, drying the film, contacting the film after the drying with a supercritical fluid to remove the pore-generating material; and baking the film after the removal of the pore-generating material.

Abstract: A semiconductor device comprises, a protective element on a substrate; a low-k dielectric film opposite the protective element and having mechanical strength smaller than a silicon oxide film; a mesh wiring opposite the protective element and in the low-k dielectric film, the mesh wiring including power supply wirings and ground wirings arranged in a mesh, the mesh wiring being electrically connected to the protective element; a silicon oxide film on the mesh wiring and the low-k dielectric film; and a bonding pad on the silicon oxide film and opposite the mesh wiring.

Abstract: A semiconductor apparatus comprises a first semiconductor device and a second semiconductor device. The first semiconductor device includes: a semiconductor layer having a p-type channel area; an n-type source area, and an n-type drain area; a first gate insulating film provided on the p-type channel area; and a first gate electrode provided on the first gate insulating film containing a first metallic element and nitrogen. The second semiconductor device includes: a semiconductor layer having an n-type channel area, a p-type source area, and a p-type drain area; a second gate insulating film provided on the n-type channel area; and a second gate electrode provided on the second gate insulating film containing a second metallic element and nitrogen. A nitrogen content of the second gate electrode is higher than a nitrogen content of the first gate electrode.

Abstract: A method of forming a buried wiring in a low-k dielectric film, includes: forming a low-k dielectric film having a dielectric constant of 3 or less on an underlayer; removing the low-k dielectric film by a first width from an edge of the underlayer; forming a cap film on the low-k dielectric film, after removing the low-k dielectric film by the first width; forming a groove in the cap film and the low-k dielectric film; forming a conductive film in the groove and on the cap film; removing the conductive film by a second width, different from the first width by 1 mm or more, from the edge of the underlayer; and polishing unnecessary portions of the conductive film on the cap film, after removing the conductive film by the second width.

Abstract: A semiconductor device comprises: a substrate; a first film provided on the substrate; an insulation layer made of low-k material provided on the first film; a protection layer provided on a sidewall of a hole penetrating through the insulation layer and the first film to the substrate to cover the insulation layer, and a conducting portion filling the hole. The protection layer is more compact than the low-k material.

Abstract: A method for manufacturing a semiconductor device comprises: exposing a surface of a substrate to plasma; and forming an insulating film containing a low dielectric constant material on the surface of the substrate. A method for manufacturing a semiconductor device comprises: forming a modified layer by exposing a surface of a substrate to plasma; and forming an insulating film containing a low dielectric constant material on the modified layer. A method for manufacturing a semiconductor device comprises: forming an adhesion enhancement layer on a substrate; exposing a surface of the adhesion enhancement layer to plasma; and forming a first insulating film on the adhesion enhancement layer.

Abstract: A first insulating film, a second insulating film, a third insulating film, an antireflective film, and a resist film are formed in this order on a lower-layer wiring. After dry etching the third insulating film and the second insulating film, using the resist film as a mask, the resist film and the antireflective film are removed by ashing. Thereafter, the first insulating film is dry etched, using the third insulating film as a mask, to form a wiring trench extending to the lower-layer wiring. Dry etching uses a fluorocarbon-based gas to which at least one of hydrogen and an inert gas is added. Ashing is performed using at least one of hydrogen and an inert gas.

Abstract: A mass-production transfer support system has a mass-production transfer source managing computer for managing information generated in a trial-production process of a semiconductor device and a mass-production transfer destination managing computer for managing a mass-production process of the semiconductor device.

Abstract: A structure of test element group wiring includes, in addition to an electrode on a substrate including one or more layers of insulating films, and real wirings electrically connected to the electrode, includes dummy wirings electrically isolated from the electrode and having a portion of the same shape as the real wiring. The dummy wirings are disposed at a predetermined constant distance adjacent to the real wirings or to each other, so that the wiring rate of the real wiring relaxes the concentration difference of patterns. The distance between the real wirings is sufficient to perform pattern analysis using the OBIRCH method.

Abstract: A semiconductor device having a gate electrode on a silicon substrate via a gate insulating film is formed by laminating the gate insulating film with a silicon oxide film, formed on the silicon substrate, an Hf silicate film is formed on the silicon oxide film, and a nitrogen-containing Hf silicate film formed on the Hf silicate film, and containing Hf in a peak concentration in a range from one atomic % to thirty atomic %, and nitrogen in a peak concentration in a range from ten atomic % to thirty atomic %.

Abstract: A method of fabricating a semiconductor device includes forming a metal wire on a substrate, forming an interlayer insulating film on the metal wire, forming a resist pattern on the interlayer insulating film, selectively etching the interlayer film to form a trench or via-hole in the interlayer insulating film and reaching the metal wire, and ashing, using a reducing gas, to remove the resist pattern.

Abstract: A catalytic CVD equipment comprises: a vacuum chamber; a stage; a first catalyzer; and a second catalyzer. The stage holds a substrate in the vacuum chamber. The first catalyzer is provided in the vacuum chamber and has a bar member arranged substantially in parallel to a major surface of the substrate. The second catalyzer is provided in the vacuum chamber, and has a bar member arranged at a tilted angle to the major surface of the substrate. A thin film is deposited on the substrate held on the stage by introducing a source gas, by heating the first and the second catalyzer, and by decomposing the gas in the vacuum chamber under a low pressure.

Abstract: A semiconductor device comprises a semiconductor substrate and an interlayer interconnection structure provided on the semiconductor substrate. The interlayer interconnection structure includes a porous insulation film and a conductive part of a conductive material containing a metal as a major component. A volume occupation ratio of pores of a diameter greater than 0.6 nanometers is less than 30% in the porous insulation film.

Abstract: An insulating-film composition containing an insulating-film precursor and a pore-generating material is applied onto a surface of a semiconductor substrate, and a first heat treatment is performed to polymerize the insulating-film precursor without vaporizing the pore-generating material, to form a non-porous insulating film. Next, a resist pattern is formed on the non-porous insulating film, and dry etching is performed, using the resist pattern as a mask, to form a trench in the non-porous insulating film. After removing the resist pattern by ashing, the surface of the semiconductor substrate is cleaned. Next, a second heat treatment is performed to remove the pore-generating material from the non-porous insulating film and to form a porous insulating film. Thereafter, a copper layer is deposited in the trench on a barrier-metal film to form copper wiring.

Abstract: In an exposure step, a combination of a first photomask and a second mask is used. The first mask has a real pattern corresponding to the pattern actually formed on the film to be processed, and a dummy pattern added for controlling pattern pitch in the first photomask within a prescribed range; and the second photomask has a pattern isolating a real-pattern-formed region from a dummy-pattern-formed region. In forming the pattern, after forming a film to be processed on a substrate, a first mask is formed on the film to be processed, by lithography, using the first photomask, and a second mask is formed on the film to be processed, by lithography, using the second photomask. Thereafter, the film to be processed is etched and removed using the first and second masks as masks to form the pattern.

Abstract: An exposure method includes forming a resist film on a substrate to be processed, forming a top anti-reflection coating on the resist film, and irradiating the resist film with exposure light through the top anti-reflection coating. Forming the top anti-reflection coating includes adjusting refractive index and thickness of the top anti-reflection coating to increase a ratio of s-polarized light to p-polarized light in the exposure light entering the resist film.