Patents Assigned to Semiconductor Leading Edge Technologies, Inc.
  • Publication number: 20040238895
    Abstract: A SiO2 film serving as a gate dielectric film is formed on a silicon substrate. A seed Si film is formed on the gate dielectric film. A thin SiGe film of a thickness of 50 nm or less is formed on the seed Si film at a temperature between 450° C. and 494° C., and a thin cap Si film of a thickness of 0.5 nm to 5 nm is continuously formed on the thin SiGe film at the same temperature.
    Type: Application
    Filed: May 7, 2004
    Publication date: December 2, 2004
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Akiyoshi Mutou
  • Publication number: 20040235293
    Abstract: After forming a stopper film on a semiconductor substrate having a copper wiring layer therein, an interlayer insulating film made of a low dielectric constant material is formed on the stopper film. Then, after forming a capping film on the interlayer insulating film, a resist film having a predetermined pattern is formed on the capping film. The capping film and the interlayer insulating film are etched using the resist film as a mask to form an opening reaching the stopper film. After that, the stopper film exposed by the opening is etched, with the resist film left in place, to form a via hole. Then, the resist film is removed by ashing.
    Type: Application
    Filed: May 20, 2004
    Publication date: November 25, 2004
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Kazuaki Inukai, Atsushi Matsushita
  • Patent number: 6817822
    Abstract: Atmosphere inside a wafer carrier is purged through an open face of the wafer carrier, in the state where a carrier door constituting a face of the wafer carrier is opened by a load port door. Purging is carried out by partitioning a mini-environment with an upper wall surface, a lower wall surface, and an EFEM door into a predetermined space adjacent to the open face, by discharging gas from the predetermined space through an exhaust opening, and by supplying an inert gas or a dry air from a gas supply port into the predetermined space.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: November 16, 2004
    Assignee: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Kenji Tokunaga
  • Publication number: 20040222530
    Abstract: A low-k dielectric film is formed on an entire surface of a substrate having a pad region and a circuit region. A resist pattern is formed on the low-k dielectric film, and an opening is formed in the low-k dielectric film of the pad region using the resist pattern as a mask. A silicon oxide film having strength higher than the low-k dielectric film is formed in the opening by liquid-phase deposition. Wirings are formed in the silicon oxide film of the pad region and in the low-k dielectric film of the circuit region using the damascene method.
    Type: Application
    Filed: March 23, 2004
    Publication date: November 11, 2004
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Hong-Jae Shin
  • Publication number: 20040211756
    Abstract: A substrate having a film to be etched is held on a rotating stage. While rotating the substrate, a chemical solution containing an etchant is supplied onto the substrate from a nozzle. A lamp house with a drive unit is positioned so that the distance between the substrate and a glass window of the lamp house becomes 2 to 5 mm, the lamp house accommodating a lamp generating ultraviolet light. The ultraviolet light irradiates the film through the chemical solution. The ultraviolet light has a higher energy than the binding energy of constituent molecules of the film.
    Type: Application
    Filed: January 28, 2004
    Publication date: October 28, 2004
    Applicants: Semiconductor Leading Edge Technologies, Inc., Ushio Denki Kabushiki Kaisha
    Inventors: Satoshi Kume, Hirotomo Nishimori
  • Publication number: 20040213911
    Abstract: After applying a film-forming composition containing a polysiloxane, a pore-forming agent, an onium salt, and a solvent onto a semiconductor substrate, the solvent is evaporated from the film-forming compositions in a first heat treatment. Then, a second heat treatment is carried out in an inert-gas atmosphere to promote the polymerization of the polysiloxane and thus form a polysiloxane resin film. Thereafter, a third heat treatment is carried out in an oxidizing-gas ambient to form pores in the polysiloxane resin film.
    Type: Application
    Filed: March 30, 2004
    Publication date: October 28, 2004
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Kaori Misawa, Isao Matsumoto, Naofumi Ohashi, Koichi Abe, Haruaki Sakurai
  • Publication number: 20040209194
    Abstract: A substrate supporting film to be etched is held on a rotating stage. Ultraviolet light having a wavelength of 200 nm or shorter radiated from first lamps irradiates the film in air, thereby removing organic coatings from the film and making the surface of the film hydrophilic. A chemical solution applied to the hydrophilic film while rotating the substrate. Ultraviolet light having a wavelength longer than 200 nm is radiated from second lamps and onto the film through the chemical solution.
    Type: Application
    Filed: March 11, 2004
    Publication date: October 21, 2004
    Applicants: Semiconductor Leading Edge Technologies, Inc., Ushio Denki Kabushiki Kaisha
    Inventors: Satoshi Kume, Nobuyuki Hishinuma, Hiroshi Sugahara
  • Patent number: 6803170
    Abstract: A resist composition comprises: at least one type of a first compound having two or more intramolecular adamantyl structures represented by the chemical formula 1 below; a base resin; and a second compound which generates an acid by active beam irradiation. wherein X is —(OCO)m—(CH2)n—(COO)m—, where m=0 or 1 and n=0, 1, 2 or 3 provided when n=0, m=0; and Y and Z are H, OH, F, Cl, Br, R or COOR, where Y may be Z, or Y and Z may be introduced in a single adamantyl structure and R represents a straight or branched alkyl group having 1 to 8 carbon atoms.
    Type: Grant
    Filed: August 10, 2001
    Date of Patent: October 12, 2004
    Assignees: Semiconductor Leading Edge Technologies, Inc., Idemitsu Petrochemical Co., Ltd.
    Inventors: Minoru Toriumi, Isao Satou, Hiroyuki Watanabe, Shunji Katai, Shintaro Suzuki
  • Publication number: 20040198068
    Abstract: An insulating film is formed on a semiconductor base material, the insulating film being predominantly composed of organic siloxane and containing an organic component which has no chemical bond to the organic siloxane. Plasma treatment is applied to the insulating film to remove the organic component and form a modifying layer on a surface of the insulating film.
    Type: Application
    Filed: March 19, 2004
    Publication date: October 7, 2004
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Toru Yoshie
  • Publication number: 20040196447
    Abstract: Each of patterns on two types of photomasks, including identical central pattern portions, each having a line pattern on the center of a substrate, and peripheral pattern portions around the central pattern portions, and having distances between the central pattern portion and the peripheral pattern portion different from each other, is transferred onto a wafer. Thereafter, each line width of the transferred patterns corresponding to the line pattern of each photomask is measured. The difference between each of line widths is obtained, from which the flare rate is calculated.
    Type: Application
    Filed: March 17, 2004
    Publication date: October 7, 2004
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Kunio Watanabe
  • Publication number: 20040191997
    Abstract: A method for manufacturing a semiconductor device includes forming a first insulating film on a substrate, forming a second insulating film on the first insulating film, and forming a gate electrode on the second insulating film. Forming the second insulating film includes supplying film-forming materials and adsorbing the film-forming materials on the first insulating film, purging the film-forming materials that have not been adsorbed, supplying oxidants to oxidize the adsorbed film-forming materials, and purging the oxidants that have not contributed to oxidization. Forming the second insulating film is repeated in cycles, continuously, and the purging time of the oxidants in an initial number of the cycles is longer than the purging time of the oxidants in cycles following the initial number of cycles.
    Type: Application
    Filed: March 11, 2004
    Publication date: September 30, 2004
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventors: Takaaki Kawahara, Kazuyoshi Torii
  • Publication number: 20040188778
    Abstract: A semiconductor device includes a first insulating film on a silicon substrate and a second insulating film on the first insulating film. The first insulating film is a silicon oxide film having a thickness of 1 nm or less and a suboxide content of 30% or less. The second insulating film is a high dielectric constant insulating film.
    Type: Application
    Filed: March 29, 2004
    Publication date: September 30, 2004
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Tomonori Aoyama
  • Publication number: 20040188675
    Abstract: A semiconductor device comprises an inorganic film on a semiconductor substrate, an intermediate film on the inorganic film and containing silicon, and an organic film on the intermediate film and containing fluorine. The organic film is made of a fluorinated arylene film.
    Type: Application
    Filed: March 9, 2004
    Publication date: September 30, 2004
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Naruhiko Kaji
  • Patent number: 6780547
    Abstract: In a halftone phase shifting photomask 108, having a pattern of halftone phase shifting film 102 containing at least chromium and fluorine, the halftone phase shifting film is heat-treated at a temperature between 250° C. and 500° C. so that a change of the optical property of the film produced by the application of excimer laser for exposure to the film is decreased.
    Type: Grant
    Filed: April 3, 2001
    Date of Patent: August 24, 2004
    Assignees: Dainippon Printing Co., Ltd., Semiconductor Leading Edge Technologies, Inc.
    Inventors: Toshiaki Motonaga, Norihito Ito, Chiaki Hatsuta, Junji Fujikawa, Naoya Hayashi, Toshio Onodera, Takahiro Matsuo, Toru Ogawa, Keisuke Nakazawa
  • Publication number: 20040150075
    Abstract: A porous MSQ is formed on a silicon substrate, and an SiC mask is formed thereon. Plasma etching using the SiC mask as a mask is performed to form a trench in the porous MSQ. A fluorinated polyxylilene film is formed on the entire surface of the substrate 1 including the side surfaces of the trench, and the unnecessary fluorinated polyxylilene film formed on the area other than the side surfaces of the trench is removed. A barrier-metal film and a seed Cu layer are formed in the trench and a Cu is deposited.
    Type: Application
    Filed: December 16, 2003
    Publication date: August 5, 2004
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Naruhiko Kaji
  • Patent number: 6769908
    Abstract: A wafer heat-treatment system for processing a wafer by a high-temperature heat-treatment process and cooling the heat-treated wafer, comprises walls surrounding a closed space placing the wafer and having a hollow sealing a gas therein, and a pressure-regulating unit connecting to the hollow for regulating pressure in the hollow. Hence, the wafer heat-treatment system reduces power consumption by heating lamps by carrying out an evacuating process before the high-temperature heat-treatment process, and shortens the time necessary for the cool down process by a pressurizing process that is carried out after the completion of the high-temperature heat-treatment process.
    Type: Grant
    Filed: February 6, 2002
    Date of Patent: August 3, 2004
    Assignee: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Yoshimasa Kawase
  • Patent number: 6760115
    Abstract: A carrier shape measurement device includes: a stage which supports a carrier which is to be a subject of measurement; and a measurement section which measures a shape of the carrier, and the stage comprises kinematic coupling pins to support the carrier by a kinematic coupling.
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: July 6, 2004
    Assignees: Nikon Corporation, Semiconductor Leading Edge Technologies, Inc.
    Inventors: Fusao Shimizu, Atsuhiro Fujii
  • Patent number: 6731375
    Abstract: In the present invention, a substrate with exposure light from an exposure light source is irradiated before a projection exposure beforehand. A reflectance of this exposure light from the substrate is measured. An appropriate intensity of exposure light for the substrate is determined by referring to the reflectance. Then, a mask pattern is projected onto the substrate by irradiating with exposure light of the determined intensity.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: May 4, 2004
    Assignee: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Tetsuro Hanawa
  • Patent number: 6726799
    Abstract: A focus ring is disposed along a circumference of a semiconductor substrate on a lower electrode. A sensor measures a position of an upper surface of the focus ring, and a drive mechanism 6 drives the focus ring vertically. A controller adjusts the position of the upper surface of the focus ring to a desired position by driving the drive mechanism on the basis of a result of measurement by the sensor.
    Type: Grant
    Filed: November 7, 2001
    Date of Patent: April 27, 2004
    Assignee: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Osamu Koike
  • Patent number: 6716761
    Abstract: A resist pattern is formed on a film to be processed using a lithography technique. The line width of the resist pattern is narrowed using a slimming technique. Thereafter, the pattern of a first film to be processed is formed in the space that has been widened by slimming, utilizing the phenomenon in which anisotropic etching under a reduced pressure accelerates the etching rate in the vicinity of the side of the line of the pattern compared to other areas. An underlying second film to be processed is etched using the first film to be processed as a mask. Thereby the pattern of the second film to be processed that has a pitch ½ the lithography pattern is formed.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: April 6, 2004
    Assignee: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Akira Mitsuiki