Patents Assigned to Semiconductor Leading Edge Technologies, Inc.
  • Publication number: 20040059033
    Abstract: A composition for anti-reflective coatings comprising a polymer that contains fluorine and a solvent that dissolves the polymer is applied onto a semiconductor substrate to form an anti-reflective coating. Next, a resist film containing fluorine is formed on the anti-reflective coating. Then, the resist film is irradiated by exposure light to form resist patterns.
    Type: Application
    Filed: October 2, 2003
    Publication date: March 25, 2004
    Applicant: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Minoru Toriumi
  • Patent number: 6709791
    Abstract: The invention relates to a halftone phase shift photomask whose transmittance and phase angle remain unchanged even when irradiated with an excimer laser used for exposure over an extended period of time, and a blank therefor, and provides a halftone phase shift mask 108 comprising a pattern of halftone phase shift film 102 containing at least chromium and fluorine on a transparent substrate 101, wherein optical characteristic changes upon irradiation with an exposure excimer laser have been reduced by patterning a film irradiated with light 109 having a wavelength substantially absorbed by halftone phase shift film 102.
    Type: Grant
    Filed: April 10, 2001
    Date of Patent: March 23, 2004
    Assignees: Dai Nippon Printing Co., Ltd., Semiconductor Leading Edge Technologies, Inc.
    Inventors: Hiroshi Mohri, Toshiaki Motonaga, Chiaki Hatsuta, Norihito Ito, Naoya Hayashi, Toshio Onodera, Takahiro Matsuo, Toru Ogawa, Keisuke Nakazawa
  • Patent number: 6652212
    Abstract: A cylinder of the invention can precisely send out a piston rod 3 into four different positions and comprises: a spring receiving member 14 placed coaxially with piston rod 3 in a piston room (I-II) of a cylinder tube 2 so that the movement of spring receiving member 14 is limited by one end of the piston room; a first spring member 15 to separate the spring receiving member from the piston; a stopper 8 formed on piston rod 3 to limit spring receiving member 14 from moving in the opposite direction to piston 4, a hollow 9 formed on the periphery of piston rod 3 at farther position from piston 4 than stopper 8; and a stop pin 11 installed in the cylinder tube to be pressed in the direction of hollow 9 by a second spring member 12 to engage with hollow 9, wherein the movable length of piston rod 9 while stop pin 11 is engaged with hollow 9 is larger than movable distance of spring receiving member 14 from the piston. A load port and a production system of this invention are constructed using the cylinder.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: November 25, 2003
    Assignees: CKD Corporation, Semiconductor Leading Edge Technologies, Inc., Rorze Corporation
    Inventors: Shinyo Kimoto, Kenji Tokunaga, Katsunori Sakata, Norio Kajita
  • Patent number: 6611317
    Abstract: An exposure apparatus, wherein at least one of optical members constituting an exposure light source system, an illuminating optical system, a photomask and a projection optical system, is made of a synthetic quartz glass for an optical member, which has an absorption coefficient of 0.70 cm−1 or less at a wavelength of 157 nm and an infrared absorption peak attributable to SiOH stretching vibration at about 3640 cm−1.
    Type: Grant
    Filed: February 16, 2001
    Date of Patent: August 26, 2003
    Assignees: Asahi Glass Company, Limited, Semiconductor Leading Edge Technologies, Inc.
    Inventors: Tohru Ogawa, Hideo Hosono, Shinya Kikugawa, Yoshiaki Ikuta, Akio Masui, Noriaki Shimodaira, Shuhei Yoshizawa
  • Patent number: 6586163
    Abstract: There is described a method of forming a fine pattern aimed at depositing a silicon-nitride-based anti-reflection film which is stable even at high temperature and involves small internal stress. The method is also intended to preventing occurrence of a footing pattern (a rounded corner) in a boundary surface between a photoresist and a substrate at the time of formation of a chemically-amplified positive resist pattern on the anti-reflection film. The method includes the steps of forming a silicon-nitride-based film directly on a substrate or on a substrate by way of another layer; and forming a photoresist directly on the silicon-nitride-based film or on the silicon-nitride-based film by way of another layer. The silicon-nitride-based film is deposited while the temperature at which the substrate is to be situated is set so as to fall within the range of 400 to 700° C., through use of a plasma CVD system.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: July 1, 2003
    Assignees: Semiconductor Leading Edge Technologies Inc., ASM Japan K.K.
    Inventors: Ichiro Okabe, Hiroki Arai
  • Patent number: 6535781
    Abstract: In an apparatus for inspecting and analyzing a particle on a wafer, which causes defect of an integrated circuit, the invention aims to improve the precision of the coordinate of the particle to facilitate the analysis of the particle. As a result, the generation of the particle can be reduced and the yield of the integrated circuit can be increased. A coordinate modifying apparatus of the invention includes a parameter calculating unit 40 for calculating a coordinate modification parameter, a parameter memory 60 for storing the coordinate modification parameter, and a coordinate modifying unit 70 for correcting the coordinate using the coordinate modification parameter.
    Type: Grant
    Filed: March 8, 2000
    Date of Patent: March 18, 2003
    Assignee: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Toshiaki Tsutsumi
  • Publication number: 20030046998
    Abstract: A substrate-container measuring device has a kinematic plate 10 having securing pins 12 provided at positions defined by the SEMI standards. There is provided an optical distance-measuring sensor 14, in which a relative position between the optical distance-measuring sensor 14 and the kinematic plate 10 is fixed. A substrate-container measuring jig 20 is placed on the kinematic plate 10. The substrate-container measuring jig 20 has a base plate 22 to be placed on the kinematic plate 10, and a slide plate 24 that is slidable over the base plate 22. The base plate 22 has a group of grooves which uniquely determine a relative position between the base plate 22 and the kinematic plate 10 as a result of being fitted with the corresponding securing pins 12.
    Type: Application
    Filed: August 2, 2002
    Publication date: March 13, 2003
    Applicant: SEMICONDUCTOR LEADING EDGE TECHNOLOGIES, INC.
    Inventor: Hisaharu Seita
  • Publication number: 20030049101
    Abstract: A substrate container having substrates stored therein and sealed with a door is placed onto a load port apparatus provided on a substrate processing system, and a door of the load port apparatus is docked with the door of the substrate container. An inside of the substrate container is pressurized before opening of the door of the substrate container before the door of the substrate container is opened and the substrates stored in the substrate container is transported to the substrate processing system.
    Type: Application
    Filed: August 16, 2002
    Publication date: March 13, 2003
    Applicant: SEMICONDUCTOR LEADING EDGE TECHNOLOGIES, INC.
    Inventor: Hisaharu Seita
  • Publication number: 20030031537
    Abstract: Atmosphere inside a wafer carrier is purged through an open face of the wafer carrier, in the state where a carrier door constituting a face of the wafer carrier is opened by a load port door. Purging is carried out by partitioning a mini-environment with an upper wall surface, a lower wall surface, and an EFEM door into a predetermined space adjacent to the open face, by discharging gas from the predetermined space through an exhaust opening, and by supplying an inert gas or a dry air from a gas supply port into the predetermined space.
    Type: Application
    Filed: July 30, 2002
    Publication date: February 13, 2003
    Applicant: SEMICONDUCTOR LEADING EDGE TECHNOLOGIES, INC.
    Inventor: Kenji Tokunaga
  • Publication number: 20030009904
    Abstract: When atmosphere inside a wafer carrier is replaced by introducing a gas into the wafer carrier from a gas inlet provided to the wafer carrier that can accommodate wafers. At the same time, the atmosphere inside the wafer carrier is sucked to make an inside pressure negative relative to an outside pressure.
    Type: Application
    Filed: July 10, 2002
    Publication date: January 16, 2003
    Applicant: SEMICONDUCTOR LEADING EDGE TECHNOLOGIES, INC.
    Inventor: Kenji Tokunaga
  • Publication number: 20020182037
    Abstract: A substrate processing apparatus for providing predetermined processing to wafers brought in through the load port door comprises in the front of the load port door a load port table on which a wafer carrier accommodating a plurality of wafers is placed, and a shield plate is provided so as to surround the load port table.
    Type: Application
    Filed: March 7, 2002
    Publication date: December 5, 2002
    Applicant: SEMICONDUCTOR LEADING EDGE TECHNOLOGIES, INC.
    Inventors: Shinyo Kimoto, Kenji Tokunaga, Seokhyun Kim, Terumi Muguruma, Yoshiaki Yamada, Shinichi Watanabe, Masahiro Nishi
  • Patent number: 6473996
    Abstract: In a load port mechanism of a substrate treatment unit, protuberances are provided on a sealing surface formed along a door with which a wafer carrier is to dock, or on a sealing surface formed around the door of the wafer carrier. The wafer carrier door is faced with the load port door with the protuberances therebetween, thereby separating the sealing surface of the substrate treatment unit from the sealing surface of the wafer carrier by only a predetermined distance. Thus, there is formed a channel along which clean air flows from the inside of the substrate treatment unit to the outside thereof. The load port structure and the wafer carrier structure improve the reliability of opening/closing action of the wafer carrier and prevent entry of extraneous particles into the treatment unit with sufficient reliability, and enable high-yield production of integrated circuits.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: November 5, 2002
    Assignee: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Kenji Tokunaga
  • Publication number: 20020148135
    Abstract: A wafer heat-treatment system for processing a wafer by a high-temperature heat-treatment process and cooling the heat-treated wafer, comprises walls surrounding a closed space placing the wafer and having a hollow sealing a gas therein, and a pressure-regulating unit connecting to the hollow for regulating pressure in the hollow. Hence, the wafer heat-treatment system reduces power consumption by heating lamps by carrying out an evacuating process before the high-temperature heat-treatment process, and shortens the time necessary for the cool down process by a pressurizing process that is carried out after the completion of the high-temperature heat-treatment process.
    Type: Application
    Filed: February 6, 2002
    Publication date: October 17, 2002
    Applicant: SEMICONDUCTOR LEADING EDGE TECHNOLOGIES, INC.
    Inventor: Yoshimasa Kawase
  • Patent number: 6446645
    Abstract: There are provided an system for evaluating the amount of particles, a dip cleaning system, and a method of evaluating the amount of particles adhering to a substrate, which enable high-precision quantitative evaluation of the amount of particles suspended in a liquid without use of a monitor substrate, which enable easy determination of the correlation between the amount of particles suspended in the liquid and the amount of particles adhering to the substrate which is an object of cleaning, and which enable low-cost and highly-reliable cleaning evaluation. A residual liquid recovery pan for recovering a residual liquid interposed and a residual liquid quantitative measurement bath for measuring the amount of submerged particles is interposed, between the first substrate treatment bath and the second substrate treatment bath.
    Type: Grant
    Filed: June 1, 2000
    Date of Patent: September 10, 2002
    Assignee: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Minoru Doi
  • Publication number: 20020096189
    Abstract: A cleaning apparatus is provided with a processing bath to be filled with a cleaning chemical, an ultrasonic oscillator, and a retainer for holding a substrate to be immersed into a cleaning chemical. The front surface of the substrate is cleaned while ultrasonic waves are radiated from the ultrasonic oscillator onto the back surface of the substrate.
    Type: Application
    Filed: January 18, 2002
    Publication date: July 25, 2002
    Applicant: SEMICONDUCTOR LEADING EDGE TECHNOLOGIES, INC.
    Inventor: Satoshi Kume
  • Publication number: 20020094688
    Abstract: A resist pattern is formed on a film to be processed using a lithography technique. The line width of the resist pattern is narrowed using a slimming technique. Thereafter, the pattern of a first film to be processed is formed in the space that has been widened by slimming, utilizing the phenomenon in which anisotropic etching under a reduced pressure accelerates the etching rate in the vicinity of the side of the line of the pattern compared to other areas. An underlying second film to be processed is etched using the first film to be processed as a mask. Thereby the pattern of the second film to be processed that has a pitch ½ the lithography pattern is formed.
    Type: Application
    Filed: December 21, 2001
    Publication date: July 18, 2002
    Applicant: SEMICONDUCTOR LEADING EDGE TECHNOLOGIES, INC.
    Inventor: Akira Mitsuiki
  • Publication number: 20020092964
    Abstract: A water edge exposure apparatus is provided with an optical section for radiating exposure light onto the edge of a semiconductor wafer. The optical section is provided with a focus sensor for sensing a distance from the lower end of the optical section to the edge of the semiconductor wafer. There is provided a position control mechanism for moving the optical section vertically on the basis of a value detected by the focus sensor such that the distance matches a focal distance of the optical section.
    Type: Application
    Filed: January 7, 2002
    Publication date: July 18, 2002
    Applicant: SEMICONDUCTOR LEADING EDGE TECHNOLOGIES, INC.
    Inventor: Jeong Yeal Kim
  • Publication number: 20020076628
    Abstract: In the present invention, a substrate with exposure light from an exposure light source is irradiated before a projection exposure beforehand. A reflectance of this exposure light from the substrate is measured. An appropriate intensity of exposure light for the substrate is determined by referring to the reflectance. Then, a mask pattern is projected onto the substrate by irradiating with exposure light of the determined intensity.
    Type: Application
    Filed: November 8, 2001
    Publication date: June 20, 2002
    Applicant: SEMICONDUCTOR LEADING EDGE TECHNOLOGIES, INC.
    Inventor: Tetsuro Hanawa
  • Publication number: 20020072240
    Abstract: A focus ring is disposed along a circumference of a semiconductor substrate on a lower electrode. A sensor measures a position of an upper surface of the focus ring, and a drive mechanism 6 drives the focus ring vertically. A controller adjusts the position of the upper surface of the focus ring to a desired position by driving the drive mechanism on the basis of a result of measurement by the sensor.
    Type: Application
    Filed: November 7, 2001
    Publication date: June 13, 2002
    Applicant: SEMICONDUCTOR LEADING EDGE TECHNOLOGIES, INC.
    Inventor: Osamu Koike
  • Patent number: 6379219
    Abstract: At least two elastic wave sensors are disposed in contact with a workpiece such as a microstructure or an optical structure. Elastic waves generated during chemical mechanical polishing of the workpiece are monitored by using the elastic wave sensors. Chemical mechanical polishing conditions are set to achieve uniform chemical mechanical polishing, or an ending point of the chemical mechanical polishing is set based on the monitored signal by the elastic wave sensors, and a process is carried out for chemical mechanical polishing. By the process, a workpiece is polished uniformly to flatten steps in the workpiece or to flatten surface defects of a structure. Alternatively, by the process, a workpiece having a laminated structure is polished up to an interface of the laminated structure.
    Type: Grant
    Filed: May 24, 2000
    Date of Patent: April 30, 2002
    Assignee: Semiconductor Leading Edge Technologies, Inc.
    Inventor: Takayuki Oba