Abstract: Historical steps such as processes of fabrication are each assigned a predetermined character code. Character codes are gathered and arranged in chronological order of the fabrication processes for their classification. Using such a classification method, a database is built to include records each storing a plurality of measured data and accommodating data fields for retaining historical data.
Type:
Grant
Filed:
August 10, 1998
Date of Patent:
March 26, 2002
Assignee:
Semiconductor Leading Edge Technologies, Inc.
Abstract: The present invention provides a method for wiring, which plugs conductive material sufficiently into a via hole produced in dielectronics (hereinafter, referred to as “a via hole”) and prevents generating a void. The via hole is made through a via hole patterning step and a cleaning step. At a surface treatment step, substance having chemical affinity (active site) is adsorbed to the surface of the via hole. Next, an electron donative layer is made by depositing substance having an electron donative characteristic on the active sites acting as cores at an electron donative layer formation step. Then, the wiring material is plugged at a via hole plug step.
Type:
Grant
Filed:
March 31, 2000
Date of Patent:
March 12, 2002
Assignee:
Semiconductor Leading Edge Technologies, Inc.
Abstract: A resist composition comprises: at least one type of a first compound having two or more intramolecular adamantyl structures represented by the chemical formula 1 below; a base resin; and a second compound which generates an acid by active beam irradiation.
Type:
Application
Filed:
August 10, 2001
Publication date:
February 21, 2002
Applicant:
Semiconductor Leading Edge Technologies, Inc.