Abstract: A process for the manufacturing of integrated circuits provides for forming contacts between a conductive material layer and first doped regions of a semiconductor substrate in a self-aligned manner to edges of an insulating material layer which defines active areas of the integrated circuit wherein the doped regions are formed, and second doped regions of the same conductivity type as the first doped regions under the first doped regions, the second doped regions extending partially under the edges of the insulating material layer to prevent short-circuits between the conductive material layer and the semiconductor substrate. The second doped regions are formed by means of implantation of dopants along directions slanted with respect to an orthogonal direction to a surface of the semiconductor substrate at angles and with an energy sufficiently high to make the dopants penetrate in the semiconductor material deeper than the first doped regions and under the edges of the insulating material layer.

Abstract: A process for the formation of a device edge morphological structure for protecting and sealing peripherally an electronic circuit integrated in a major surface of a substrate of semiconductor material. The electronic circuit is of the type that calls for formation above the major surface of at least one dielectric multilayer. The dielectric multilayer includes a layer of amorphous planarizing material having a continuous portion extending between two contiguous areas with a more internal first area and a more external second area in the morphological structure. The device edge morphological structure includes in the substrate an excavation on the side of the major surface at the more internal first area of the morphological structure in a zone in which is present the continuous portion of the dielectric multilayer.

Abstract: The present invention relates to a method for characterizing at least one photorepeater and a same set of patterns implemented on several regions of a wafer, including the steps of making a standard reticle defining at least one first series of at least three identical reference patterns, which are not aligned; successively exposing several regions of a standard wafer by varying the illumination dose from one region to another; measuring the respective dimensions of the reference patterns reproduced on the different regions of the wafer to determine, for each illumination does, the mean dimension of the reference patterns; and performing a linear interpolation of these mean dimensions.

Abstract: A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.

Abstract: An integrated circuit includes a high-voltage output stage. The high-voltage output stage, in turn, comprises a first MOS transistor, a second MOS transistor, a current source and a diode. This high-voltage output stage can be improved by the addition of a third MOS transistor, a first bipolar transistor and, possibly, a second bipolar transistor.

Abstract: A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a plurality of elementary functional units, a first insulating material layer placed above the semiconductor material layer and a conductive material layer placed above the first insulating material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes a first elongated window in the conductive material layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a second insulating material layer disposed above the conductive material layer and disposed along elongated edges of the first elongated window.

Abstract: An integrated circuit comprises a memory zone, a test mode and at least one binary type of lock, said lock when it is in a first state permitting the operation of the integrated circuit in the test mode and when it is in a second state prohibiting the operation of the integrated circuit in test mode, wherein the integrated circuit comprises a dysfunction circuit that works when the lock is in the first state, said dysfunction circuit preventing the memory from working normally. The use of a dysfunction circuit makes it possible to reveal components whose test locks have not been activated as being defective.

Abstract: A method for fabricating a lead frame that includes a platform attached thereto for mounting a chip. A base frame is provided for mounting chips of various sizes. The base frame includes connection leads extending toward a central portion, which is substantially of the size of the smallest chip to mount. Connection leads are cut-out about the central portion to form an opening corresponding to the size of the chip to be mounted. A platform is soldered to at least two support leads to form the lead frame.

Abstract: The invention provides a method for producing wiring and contacts in an integrated circuit including the steps of forming insulated gate components on a semiconductor substrate; applying a photo-reducible dielectric layer to cover the substrate; etching holes and forming contacts; photo-reducing the dielectric to increase its conductivity; covering the resulting structure with an interconnect layer; etching the interconnect layer to define wiring in electrical contact with the contacts; and oxidizing the dielectric to reduce its conductivity.

Abstract: A monolithically integrated power device for driving electrical loads includes a power stage having a high-voltage bipolar transistor and a low-voltage auxiliary transistor cascade-connected and inserted between a first power supply terminal and a second power supply terminal of the device. The power device also includes a driver circuit for the power stage having an input connected to an input terminal of the device. In accordance with the present invention the device includes a circuit for protection thereof against an excessive temperature rise and controlling power down of the power stage.

Abstract: A MOS-gated power device integrated structure comprises a plurality of elementary units formed in a semiconductor material layer of a first conductivity type. Each elementary unit is formed in a body stripe of a second conductivity type. There are a plurality of body stripes of the second conductivity type extending substantially in parallel to each other and at least one source region of the first conductivity type disposed within each body stripe. A conductive gate layer is insulatively disposed over the semiconductor material layer between the body stripes in the form of a first web structure. A second web structure of the second conductivity type is formed in the semiconductor material layer and comprises an annular frame portion surrounding the plurality of body stripes and at least one first elongated stripe extending between two sides of the annular frame portion in a direction substantially orthogonal to the body stripes and that is merged at each end with the annular frame portion.

Abstract: Disclosed is a synchronization circuit that can be applied in the field of monitors and, especially, in the field of television receivers. The disclosed circuit comprises circuits to analyse and correct the horizontal and vertical synchronization signals in order to neutralize the effect of the signalling present in the horizontal synchronization signal on the working of a phase-locked loop.

Abstract: A circuit for providing a rectified voltage to a flyback switch-mode supply circuit comprises a rectifying bridge having output terminals; a primary winding of the switch-mode supply having an intermediate tap; a switch serially connected with the primary winding; the serial connection between the output terminals, of a first diode and a capacitor, the first diode being biased so as to allow the charging of the capacitor; a second diode between a first output terminal of the winding, the second and third diodes being biased so as to let the current flow towards a second terminal of the winding.

Abstract: Disclosed is an electrically modifiable, multilevel non-volatile memory including internal refresh means. If a memory with n sectors is considered, only n-1 sectors are allocated simultaneously to the storage of the data elements, the remaining sector or refresh sector is used to receive the duplicated data from one of the n-1 sectors assigned simultaneously to the storage of the data elements. After each duplication, the duplicated sector is replaced by said refresh sector and itself becomes the new refresh sector, in such a way that that all the n sectors, in turn, take part in the refresh operation.

Abstract: A circuit for the generation of an electrical signal of constant duration comprises a capacitor, a constant current generator for charging the capacitor, and a voltage comparator to compare the voltage present at the terminals of the capacitor with a reference voltage. The voltage comparator supplies at an output a digital signal dependent upon the voltage across the capacitor. The constant current generator comprises a transistor biased with a voltage between gate and source obtained as the difference between the sum of two gate-source voltages of two transistors and a gate-source voltage of another transistor.

Abstract: A multistandard rectified supply circuit comprises, across a full wave rectifying bridge, at least one storing element associated with a charge path comprising first unidirectional conductive elements of a first polarity and with a discharge path comprising second unidirectional conductive elements of a second polarity so that the storing means is differently charged and discharged. A switch cancels the effect of at least one of the first and second unidirectional elements so that the storing element is charged and discharged through a same path.

Abstract: A device for providing a high d.c. voltage supply and a low d.c. voltage supply. The device includes, in parallel, a first diode connected in series with a capacitor, a rectifier having a polarity opposite to that of the first diode, and a breakover voltage limiter. The terminals of the low d.c. voltage source correspond to the terminals of the capacitor.

Abstract: A neural cellular network for implementing a so-called Chua's circuit, and comprising at least first, second and third cells having respective first and second input terminals and respective state terminals, the first and second input terminals being to receive a first and a second reference signal, respectively, and the first cell, and the second and third cells being of mutually different types.

Abstract: System for decoding code words in the EFM-PLUS and/or EFM format in which an enumeration block makes it possible to associate in a one-to-one manner with each of the code words a numerical value from a practically continuous set of numerical values. The numerical value, possibly summed with an offset value, by an address generator, addresses a read-only memory in which are stored information codes, each of which is associated, as decoded information, with one of the code words.

Abstract: The DMOS transistor includes an n drain region, a p body region which forms, with the drain region, a junction having at least one edge portion with a small radius of curvature, an n+ source region which delimits a channel in the body region, p+ body contact regions, a gate electrode, a source and body electrode, and a drain electrode. To prevent the "snap-back" phenomenon when the junction is reverse biased with the source, body and gate electrodes short-circuited, a p+ region is associated with each of the edge portions having a small radius of curvature and is arranged so as to be closer to the associated edge portion than any part of the source region.