Abstract: A self-aligned metallization for an MOS device is described in which a first layer of tungsten is selectively deposited on the exposed silicon surfaces of the device including at least the source, drain and gate regions of the device, a layer of material providing nucleation sites for tungsten is selectively formed across insulating oxide regions of the device, and a second tungsten layer is selectively deposited on the nucleating layer and the exposed first tungsten layer to provide interconnection across the oxide regions. In addition to having a low electrical resistivity, such a metallization enables relaxed mask alignment and etching tolerance requirements, and is therefore useful in VLSI circuits.
December 8, 1988
Date of Patent:
June 26, 1990
Janet M. DeBlasi, Paulus Z. A. Van Der Putte
Abstract: A transceiver device has a transmitter circuit for transmitting data from a local data terminal to a computer network. The transmitter circuit has a voltage-to-current converter including a voltage divider with a plurality of voltage threshold taps, each voltage tap having a fixed voltage level; and a plurality of differential current switches each having first and second differential inputs, and a current differential output. Each of the first differential inputs is connected in common for receiving a voltage signal, and the second differential inputs are connected to an associated one of the voltage threshold taps. The current switch outputs are directly connected to a common node, to provide a current signal stepwise the same as the voltage signal. Preferably the common node is connected to a current amplifier including a simple filter. The output current waveform is preferably a trapezoidal waveform having matched rise and fall times.
Abstract: A circuit which expands monochrome character image patterns to color form for use in a raster scanned computer display system. Monochrome patterns are expanded from one bit per pixel to n bits per pixel. Foreground and background colors are programmable in a pattern generator which uses data from the expanded source patterns to select appropriate colors and characters for a destination pattern to be displayed. The expanded multicolor image is generated by hardware.
Abstract: A transceiver system for high speed, low bit-error rate data communications over a.c. power lines in the presence of repetitive impulse noise includes an a.c. power line coupling network, a power line communications modem, and a microprocessor with a memory and a programmed avoidance algorithm. The a.c. line coupling network includes a zero crossing circuit to detect the start of each a.c. cycle; a transient-voltage limiting front end to detect impluse noises above a threshold and minimize ringing, and a timing circuit to determine the time and duration of each impulse in each sampled a.c. cycle. The microprocessor records the start and stop times of impulses, repetitively scans several a.c. cycles and determines whether or not the impulses are periodic. For periodic impulses, the microprocessor blocks communication on the modem during the impulses, enabling the transceiver to transmit and receive between impulses.
Abstract: A non-inverting low power high speed bootstrapped buffer having a depletion mode FET device which senses a rising voltage triggers the bootstrap of a high capacitance node isolated from the input. Heavy output loading can be isolated from the bootstrap node. High resistance devices are used to make a fully static circuit.
Abstract: In a bit-mapped display system, a logical subsystem for programmable sharing of access to a memory in a computer system among a plurality of system resources wherein various modes of operation are supported by the logic and are programmably selected by the user. The use of display memory is controlled between updating and display accesses to prevent breakup of the video image while said image is being changed.
Abstract: A select buffer circuit includes a first inverter circuit, a second inverter circuit connected to the first, and a circuit for charging and discharging the base of an inverter transistor in the second inverter circuit from a node in the first inverter circuit. The charging and discharging circuit includes a Schottky diode connected to the inverter transistor, a Schottky transistor connected in series with the diode, and a resistor for coupling the base of the Schottky transistor to the node in the first inverter circuit. A bipolar multiplexer including the select buffer circuit offers the advantage of an improved output waveform.
Abstract: A method for fabricating a semiconductor device in which the base resistance is minimized to increase the speed of operation of the device. This is accomplished because the device made by the method makes it possible to form the base and emitter contacts next to each other laterally but spaced vertically.
Abstract: An on-chip regulated substrate bias voltage generator for an MOS integrated circuit includes a ring oscillator (10) for developing a true signal and its complement. The signals are applied to a charge pump (12) that includes two capacitors (C1 and C2) and a plurality of rectifiers (22, 24, and 26). The charge pump produces a substrate bias voltage (V.sub.BB) which is supplied to the gate of a depletion-mode field-effect transistor (28) whose source receives a reference voltage (V.sub.SS). The transistor forms part of a control circuit (14) coupled to the ring oscillator. In the N-channel case, the charge pumping action on the substrate drives the substrate bias negative until it reaches the sum of the reference voltage and threshold voltage of the depletion-mode transistor. This enables the control circuit to control the operation of the ring oscillator so as to regulate the substrate bias voltage.
Abstract: A protection device (14) for an integrated circuit (12) created on a semiconductor body (24 and 26) utilizes one or more semiconductor diodes (D.sub.L and/or D.sub.H) that have subsurface PN junctions (46 and/or 56) for preventing high-magnitude voltages, such as those generated by electrostatic discharge, from damaging sensitive electronic elements of a protected circuit component (16) formed from part of the body. The device is fabricated by an epitaxial layer/double buried region process.
Abstract: A semiconductor PROM contains a group of PROM cells (12) each consisting of a pair of opposing diodes oriented vertically with their common intermediate region (22 and 24) fully adjoining a recessed oxide insulating region (16). The PN junction (30) of the upper diode of each pair lies in non-monocrystalline semiconductor material. A composite buried layer consisting of buried regions (32) which adjoin the insulating region below the lower cell regions (20) and a buried web (44) which laterally surrounds each buried region is employed to improve programming efficiency as well as provide intermediate electrical connections.
Abstract: Planarized insulating layers provided with planarized contacts are formed on semiconductor devices by forming vias through an insulating layer having a generally planar exposed surface, depositing a layer of a conductive layer on this upper surface of the insulating layer in an amount at least sufficient to at least partially fill all of the vias, depositing a planarized layer on the exposed surface of the conductive layer and then etching away the planarized layer and the conductive layer by use of an etchant that removes the planarized layer and the conductive layer at substantially the same rate, until the generally planar upper surface of the insulating layer is exposed.
Abstract: A field-programmable logic architecture is centered on a single array of programmable gates that perform either logical NAND or logical NOR operations. Foldback loops can be readily programmed through the array to enable the user to achieve different numbers of logic levels.
Abstract: A semiconductor PROM containing a group of PROM cells (12) each consisting of a pair of opposing diodes oriented vertically with their common intermediate region (22) fully adjoining a recessed oxide insulating region (16) is fabricated by a process in which the insulating region serves as a mask to control the lateral extents of the dopants utilized to define the diodes. The intermediate cell regions are ion implanted to obtain maximum dopant concentration near their mid-points. This facilitates programming operation.
July 19, 1985
Date of Patent:
September 22, 1987
George W. Conner, Raymond G. Donald, Ronald L. Cline
Abstract: During the deposition of a metallic layer on an N-type semiconductive region to form a Schottky diode in a structure placed in a highly evacuated chamber, at least one selected gas is introduced into the chamber to control the forward voltage across the diode.
Abstract: A circuit for processing the control signal inputs for a control data signal decoder wherein a reference voltage and a reference current are generated for use in processing a stream of control signal bits. The control signal data stream is filtered, buffered and exponentialed. The processing serves to cancel out variations in temperature, resistance, process variations and circuit voltages to yield a stable control signal current.
Abstract: A circuit capable of simulating a transistor or a semiconductor diode with controllably adjusted voltage characteristics contains a main transistor (Q0). An input voltage (V.sub.CS) to a control system (8) is amplified with a gain set by a pair of resistors (R1 and R2) to produce a control voltage (V.sub.C) for the transistor. This downscales the forward voltage characteristics of the circuit from those of the transistor. A floating power supply (10) in series with the control electrode of the transistor permits upscaling or further downscaling of the circuit voltage range.
October 5, 1984
Date of Patent:
July 7, 1987
Johan H. Huijsing, Timothy A. Dhuyvetter
Abstract: A circuit switches with a hysteresis defined by separately controllable thresholds which can be made largely independent of temperature and fabrication conditions. The circuit contains a pair of differential portions (21 and 22) and an arithmetic component (24). The hysteresis is introduced into the circuit by using positive feedback to control the position of a switch (23) in such a manner as to change the transconductance of the circuit as it is switching.
Abstract: A pair of complementary logic gates (A and B) are used to test for faults in a group of electronic components (C1-C3) which provide respective component signals (S1-S3) indicative of their condition. One (A) of the gates ideally generates the logical OR or NOR of the component signals. The other (B) ideally generates their logical AND or NAND. The test procedure involves providing the components with information patterns that would ideally cause all the component signals to go to a logical "0" in one step and to logical "1" in another step. The actual values of the gate output signals (OA and OB) during these two steps are then compared with the respective ideal values to assess the condition of the components.