Abstract: The data processing system of the invention comprises a processor, a memory access controller and a memory hierarchy. The memory access controller is placed between the processor and the memory hierarchy and controls access thereto. The memory access controller comprises a cache controller and a translation unit which are connected in parallel to an address bus connected to the processor and by which virtual addresses are transported. The memory access controller supports segments which are unit of sharing the memory, each segment is split up into pages. The memory access controller also supports regions which contain at least one segment. The memory access controller further supports sectors, divided into blocks which are other units of sharing the memory. And the memory access controller is also provided for enabling access with I/O units.

Abstract: A technique for producing planarized semiconductor surfaces and for isolating semiconductor islands.

Abstract: A method for fabricating insulated gate field effect transistors in NMOS or CMOS with source and drain regions having lightly doped extensions wherein the source and drain regions are made with a self-aligned process and a device made in accordance with such a method.

Abstract: An input portion (4, 6) of a differential amplifier circuit amplifies a differential input signal to produce an amplified signal between a pair of terminals. A summing section contains two complementary pairs of like-polarity amplifiers (13, 14 and 19, 20). Each has a first flow electrode, a second flow electrode, and a control electrode. A substantially constant bias voltage is supplied to the control electrodes of the first pair (13, 14) whose second electrodes are respectively coupled to the second electrodes of the second pair (19, 20). Their first electrodes are respectively coupled to the terminals and to corresponding impedance elements (11, 12). The control electrodes of the second pair are coupled together to receive a voltage dependent on the voltage at the second electrode of one (13) of the first pair so as to produce a representative output signal at the second electrode of the other (14) of the first pair.

Abstract: A multi-step A/D converter of the successive approximation type utilizes a single three-position switchable current-output DAC in combination with a voltage divider, a plurality of comparators, a decoder, a successive approximation register and a control logic module to provide a high speed, high resolution A/D converter requiring fewer parts than the prior art A/D converters of this general type.

Abstract: A NOR gate consisting of a set of input FET's (Q1.sub.1 -Q1.sub.M) has a clamp (12/ Q2) that, when at least one of the input FET's is turned on, clamps the logical low level of the gate output voltage at a value which is largely constant irrespective of how many of the input FET's are conductive.

Abstract: A programmable status register arrangement which enables the status of a plurality of status registers in a system to be checked simultaneously including fusible links connected to the outputs of the status registers whereby a user of the arrangement can program it to control the transmission of status signals by the plurality of status registers.

Abstract: A ratioless, zero d.c. power dissipating FET programmable logic array including a column boost capacitor for maintaining the columns of selected AND array transistors at approximately their precharged voltage while their associated OR array transistors are being evaluated.

Abstract: A flip-flop with a built-in enable function realized by the addition of two transistors between the trigger circuit and the output nodes of the flip-flop. This embodiment of the enable function causes no increase in power dissipation and may be used in any type of flip-flop.

Abstract: A portion (28) of photosensitive material is created by an underetching/shadowing technique in such a manner as to have an extremely narrow width.

Abstract: Circuit means for recorders in which the same external pin receives a play signal, a record signal, and a noise reduction signal generated by a user. The circuit means is comprised of a differentiating means for receiving the play and record signals and differentiating between them. A memory means is connected to the differentiating means and stores an indication of the last received of the signals. A first switch means is connected to the memory means and is operable to a first condition to control the play function when the memory means indicates the play signal was last received and to a second condition to control the record function when the memory means indicates the record signal was last received. A second switch means is connected to the external pin receiving the noise reduction signal and generating an ouptut signal to turn on noise reduction means during either the play or record mode.

Abstract: A steering circuit (10) in a differential amplifier having a pair of differentially arranged input amplifiers (A1 and A2) steers current from a pair of current sources (11 and 12) in such a way as to enhance slew rate without increasing offset voltage. The steering circuit is formed with a pair of steering amplifiers (A3 and A4) arranged in a differential configuration through a pair of resistors (R3 and R4).

Abstract: A structure for an electrical interconnection suitable for a semiconductor integrated circuit is made by a process utilizing selective tungsten deposition at low pressure to form an intermediate conductive layer without significantly ablating nearby insulating material.

Abstract: In an EEPROM memory cell of the kind which relies on tunneling action through a thin oxide layer to store charge on a floating gate, the floating gate and the channel regions of the memory cell are provided with additional doping of the same kind as in the substrate in order to raise the virgin state threshold voltage of the memory cell to a high positive value, such as 4 volts. Additionally, the overlap area between the control gate and the floating gate is reduced to the extent that the capacitance between the floating gate and the control gate is substantially equal to the capacitance between the floating gate and the substrate during programming, but the effective capacitance between the floating gate and the substrate is greatly reduced during erase mode. As a result, little or no tunneling occurs during programming and the threshold voltage level is the same as the virgin threshold value of the memory cell.

Abstract: An array arrangement for EEPROMS in which each memory cell has two transistors. Selection is simplified whereby in selecting a cell all of the cells in the selected row are connected to one terminal of the writing circuit and all the cells in the selected column are connected to the other terminal. This selection process prevents any cell from being written into except the cell at the intersection of the selected row and the selected column.

Abstract: A structure having substantial surface evenness is created by a method in which an insulating layer (24) that has an upward protrusion (26) is formed on a patterned conductive layer (20) having a corresponding upward protrusion (22). A further layer (28) having a generally planar surface is formed on the insulating layer. Using an etchant that attacks the further layer much more than the insulating layer, the further layer is etched to expose at least part of the insulating protrusion. The further layer and the insulating layer (as it becomes exposed) are then etched with an etchant that attacks both of them at rates not substantially different from each other. This brings the upper surface down without exposing the conductive layer, particularly its upward protrusion.

Abstract: A frequency detector receiving two input frequencies and generating a pump-up/pump-down signal for control of a phase locked loop by matching the frequency of a voltage controlled oscillator to the frequency. The lock is independent of the phase relationship of the signals.

Abstract: An absolute-value analog-to-digital converter containing a chain of matched main absolute-value differential amplifiers (A.sub.1 -A.sub.N) has a gain control for regulating the gain of each main amplifier utilizing an auxiliary absolute-value differential amplifier (A.sub.GC) matched to the main amplifiers. An offset control in the converter drives the offsets of the amplifiers toward zero by using a further absolute-value differential amplifier (A.sub.OC) matched to the other amplifiers. The gain and offset control are implemented with suitable feedback circuitry.

Abstract: A bipolar gate has an output transistor (Q5) that switches in response to the voltage at an emitter of a drive transistor (Q2 or Q10). An active pull-off circuit (14) discharges the base of the output transistor (Q5) when it turns off. The discharge path is provided through a pull-off transistor (Q7) whose collector is coupled to the base of the output transistor. The switching of the pull-off transistor is regulated with a control circuit containing a trigger circuit and a bias circuit. The trigger circuit is coupled between the bias circuit and a collector of the drive transistor. A "kicker" circuit formed with an input transistor (QC1) and a voltage reference (18) speeds up the switching of the drive transistor.

Abstract: A sample and hold circuit contains a pair of differential amplifiers (A1 and A2) switchably arranged in series. The circiut input signal (V.sub.IN) during sample is provided to the first amplifier (A1) which is coupled to a storage capacitor (C). The second amplifier (A2) provides the circuit output signal (V.sub.OUT) during hold. Switching circuitry (S1, S2, and S3) enables the input and output signals to undergo the same transfer function in the first amplifier. The voltage offset of the first amplifier is thereby cancelled out of the output signal, while the effect of the voltage offset of the second amplifier is reduced drastically so as to provide excellent auto-zeroing.