Abstract: A method of fabricating an array of high capacity memory cells comprises forming a transfer gate over each cell area spaced from an adjacent isolation region to define a storage region in the semiconductor surface between the transfer gate and isolation region and to define a bit line region on the other side of the transfer gate; forming a shallow ion layer of first conductivity type in the storage region self-aligned with the transfer gate; forming a deep ion layer of opposite conductivity type in the storage region self-aligned with the transfer gate; forming a storage gate over a portion of the storage region spaced laterally from the transfer gate to form a gap between the storage and transfer gates; and introducing ions of the first conductivity type into the portion of the storage region defined by the gap to at least neutralize some ions in the deep ion layer.

Abstract: A cabinet for a central processing unit, made up of a card cage and refrigeration unit, for mounting and cooling electronic components on a group of vertically-aligned, closely-spaced circuit boards. A source of recirculating, forced, refrigerated air is employed to remove the heat from the highly concentrated electronic components. For ease of maintenance, the refrigeration unit and the power supply unit take the form of independently removable modules, and the removable circuit boards are mounted in a readily accessable card cage which incorporates formed card guides which facilitate card removal and insertion.

Abstract: A temperature stable voltage reference utilizes an enhancement field effect transistor and a depletion field effect transistor each connected in series with a current source. A differential amplifier has its input terminals separately connected between each of the field effect transistors and their respective current supplies. An input terminal of the field effect transistor is utilized as the reference voltage and is also connected to the gate of one of the field effect transistors, the gate of the other field effect transistor being connected to a reference potential.

Abstract: An improved read-only memory arrangement for generating a differential output signal within the memory array itself incorporates a column of reference cell transistors and a single reference bit line within the same general area occupied by the memory cell transistors and memory main bit lines. Each word line is coupled to the gate of one of the reference cell transistors as well as to the gates of the memory cell transistors lying in the same row. The reference bit line voltage is maintained substantially midway between the high and low potential levels of the main bit lines to produce a differential output voltage for sensing purposes.

Abstract: A variable impedance circuit in which nonlinearities caused by the application of a signal are substantially reduced by the use of a feedback circuit for cancelling out the added input current due to the application of the input signal. By using a feedback circuit to obtain the desired improvement in linearity, the gain of the feedback loop can be tailored to obtain the necessary impedance range and output swing in a circuit capable of operating at relatively low power supply voltages.

Abstract: A Class "B" amplifier circuit in which Class "B" conversion takes place in a converter portion of the circuit in combination with a differential amplifier input circuit, rather than in the output stage. The converter modulates the DC bias current supplied to the differential amplifier input circuit as a function of the input signal, in order to achieve Class "B" operation. The output amplifier portion of the circuit includes a pair of complementary, series-connected transistors, each of which is connected in a common-emitter configuration. The disclosed circuit provides a high input impedance and excellent dynamic range.

Abstract: A method of fabricating a double polysilicon MOS structure of reduced size employs local oxidation of polysilicon to define and isolate a first polysilicon layer. Prior to etching the first polysilicon layer, a first masking step defines one of the elements of the MOS transistor, such as the source. By selectively etching the first polysilicon layer, the isolation regions and then the other elements of the MOS transistor are defined. With only slight variations in the simplified process, either a plurality of one MOS transistor-one capacitor memory cells or a plurality of MOS transistors can be fabricated.

Abstract: A simple MOS voltage divider uses three enhancement MOS transistors, which includes one load connected to two drivers in parallel. The gate of one driver is connected to the output node, and the other two gates are connected to the supply voltage. The transistors have a common substrate.By proper choice of the transistor geometry only, the output node voltage can be made independent of the threshold and temperature variations for output voltages larger than one threshold and smaller than one-half the supply voltage. Moreover, the ratio between the output and supply voltages remains constant.

Abstract: A constant current source circuit includes a single differential amplifier having both voltage and temperature stabilization circuits. The voltage and temperature stabilization circuits operate on a feedback principle, each receiving an input from the differential amplifier, and each in turn providing a signal back to the differential amplifier to provide the desired stabilization. The resulting circuit is particularly adapted for use in battery-powered equipment, where substantial variations in both temperature and operating voltage are likely to occur.

Abstract: In a circuit including a transistor pair feeding separate loads at different load voltages, current gain modulation or Early effect is avoided by employing an operational amplifier to maintain the collector-base voltages of the transistors equal and thereby maintain their alpha current gains equal.

Abstract: Two independent power supplies for an I.sup.2 L or ISL logic array can be timed to turn on at different times by a simple RC network connected externally of the logic array. The differential timing is utilized to condition or set a bistable device in a predetermined initial desired state, without requiring an additional device terminal pin for that purpose.

Abstract: 1. In a method for forming a semiconductor structure utilizing a semiconductor body, forming a grid structure in the semiconductor body, forming a support structure upon the grid structure, removing only a portion of the semiconductor body to provide a semiconductor body which has a substantially uniform thickness in the vicinity of the grid structure and in which the grid structure does not intercept the exposed surface of the semiconductor body, and forming additional grid structure in the semiconductor body joining the first named grid structure so that islands of semiconductor material are formed in the semiconductor body which are isolated from each other and from the support structure.23.

Abstract: In a method of configuring an integrated circuit provided in a semiconductor body having a surface and spaced semiconductor circuits formed in the body, intercoupling means are formed in the body adjacent each of said circuits, and connected to said circuits. A plurality of conductive paths are formed between said intercoupling means and carried by the body. Each intercoupling means includes a plurality of semiconductor regions formed in the semiconductor body, said regions in combination capable of assuming a first low impedance condition and a second high impedance condition to thereby selectively couple each of said circuits to selected conductive paths or decouple each of said circuits from said conductive paths. In a specific embodiment of the invention a massive monolithic integrated circuit is configured using intercoupling means in combination with small scale random access memory semiconductor circuits.

Abstract: A single flip flop is integrated with MOS circuitry which enables the single flip flop to be triggered by each of several individual clocked functions without interfering with one another. The flip flop responds only to low to high transitions of each clock signal input. This is accomplished by feeding back the flip flop output to each trigger circuit in such a way as to temporarily disconnect the trigger circuit from the flip flop during the time period between two successive low to high transitions of a particular clock signal, so that the flip flop can be triggered by other clocked functions without interference from the particular clock signal.

Abstract: Selective plasma vapor etching process for performing operations on a solid body formed of at least two different materials capable of being vapor etched exposed at, at least, one surface of the body, with the body being disposed in a chamber having a partial vacuum therein. A gas plasma is created within the chamber to produce active species of atoms and molecules so that these species come into contact with the surface of the body to chemically react at least one of the materials with active species from the gas plasma to form a gas-non-gaseous chemical reaction by controlling the concentration and reaction kinetics of specific species, and by controlling the activation energy of the etching reactions to produce a difference in rates between the materials so that the etching is more selective to one material over the other. The species is also controlled by the frequency of the electromagnetic energy.

Abstract: Method for making a semiconductor structure having isolated islands of semiconductor material from a semiconductor body by forming a first layer of insulating material on a surface of the body having a first support structure upon the layer of insulating material and then forming grooves in the semiconductor body which extend to the layer of insulating material formed from the semiconductor body. A second layer of insulating material is then formed on the exposed surfaces of the islands. A second support structure is then formed on the second layer of insulating material. Thereafter, the first support structure is removed and circuit devices are fabricated in the isolated islands.

Abstract: A protective circuit arrangement for three state bus drivers, incorporating insulated gate field effect transistors, affords protection against short circuiting of the output bus. The protective circuit senses the short circuit condition at the output bus of two push-pull output transistors and feeds back a signal to the input circuit of the ON transistor which reduces the input drive to that transistor and limits the output current through that transistor to a safe value.

Abstract: A bridge circuit for a measurement bridge of the type using four impedance arms provides an output referenced to ground which is a function of the impedances in the respective arms. The bridge circuit includes an impedance bridge comprising first, second, third and fourth impedance arms connected in series loop with first, second, third and fourth bridge terminals serially defined at the connections between the respective arms. A source of constant current is connected between the first terminal and ground. A driver is connected to bridge terminals other than the output terminal. The driver is responsive to bridge terminal signals to provide a bridge output which is a function of the impedances in the respective arms.

Abstract: A temperature compensated piezoresistive transducer includes a silicon body having a major top surface and an under surface. The body has generally parallel spaced first and second elongate slots formed therein extending through said top and under surfaces to define a center portion between said slots and first and second outer portions at the outward edge of the respective slots. The center portion is adapted to receive pressure to be measured. The body has an additional slot extending through the top and bottom surfaces and extending around the first, second and center portions to define the outer periphery of a transducer membrane with portions of the body remaining to integrally support the membrane. Plural piezoresistive elements having elongate and transverse dimensions are formed on the membrane. The elements are arrayed to receive compressive and tensile stress when pressure is applied.