Abstract: A semiconductor structure, and method for fabrication, including a semiconductor body of one conductivity type having a major surface. A layer of opposite conductivity material is formed on said surface, said layer having an upper planar surface generally parallel to said major surface. Spaced first and second collector regions are carried by said layer. A third one conductivity region is formed in said layer spaced from said first and second region and extending to an exposed surface of said layer. A fourth region of opposite conductivity type is formed within said third region and extends to an exposed surface of said layer. The layer, third and forth regions form the respective regions of an opposite conductivity--one conductivity--opposite conductivity type source transistor.

Abstract: Complementary silicon gate MOS structure formed of a semiconductor body of silicon having a major surface with a first region of N conductivity type formed in the body and extending to the surface and a second region of P conductivity type formed in the body and extending to the surface. A P-channel MOS device is formed in the first region and an N-channel MOS device is formed in the second region to provide complementary devices in the body. Each of the P and N-channel devices has a polycrystalline gate structure in which the polycrystalline material is doped with a P-type impurity to make possible the matching of threshold voltages of both devices.In the method, complementary MOS devices are formed by the use of two separate etching operations on the polycrystalline material and forming relatively thick layers of silicon type material on the semiconductor body in separate operations.

Abstract: A junction field effect transistor and a bipolar transistor are merged in a single composite device disposed within a single isolation region by the use of planar processing techniques. The device includes an annular source region formed within a semiconductor body portion constituting a collector zone. Within the central portion of the collector zone circumscribed by the annular source region there is formed an emitter zone nested within a region that constitutes both the drain region of the JFET and the base zone of the bipolar transistor. An annular channel region connects the annular source region and the central drain region. An annular region forming a semiconductor junction with the annular channel adjacent to the annular source region constitutes one of two gate regions of the JFET. The other gate region is constituted by the body portion serving as the collector zone.

Abstract: A metal contact system for an IGFET having shallow source and drain includes a refractory metal silicide layer forming low resistance ohmic contact to a silicon surface, a layer on the silicide layer of another refractory metal to serve as a barrier against diffusion of the interconnect metal, and a layer of interconnect metal over the diffusion barrier layer. The refractory metal layers are deposited by sputtering platinum or platinel for the first layer and titanium-tungsten for the second layer. In metal gate construction an additional layer of chromium is used as an etch resistant mask to protect the refractory metal layers from chemical attack when removing silicon nitride after it has been used initially as an oxidation mask and later as a sputtering mask.

Abstract: Logic circuitry provides predetermined logic outputs in response to logical combinations of inputs. The circuitry includes a plurality of input devices for receiving logic inputs and capable of assuming conduction states in response to the logic levels of said inputs. At least one output device is connected to two or more input devices. Means having predetermined logic levels is provided connected intermediate the input and output devices for controlling the conduction state of the output devices as a function of the input devices and the predetermined logic levels.

Abstract: A semiconductor transducer chip is flip-chip bonded to a semiconductor interface chip, which is mounted on the ceramic package. Thermal coupling between the package and the transducer chip is minimized by the small contact area between the transducer chip and interface chip. Micron size spacing between the spring membrane in the transducer chip and the interface chip produces squeeze film damping of the spring membrane.

Abstract: In an integrated circuit, a semiconductor body having a surface, spaced semiconductor circuits formed in the body, intercoupling means formed in the body adjacent each of said circuits, and connected to said circuits. A plurality of conductive paths are formed between said intercoupling means and carried by the body. Each intercoupling means includes a plurality of semiconductor regions formed in the semiconductor body, said regions in combination capable of assuming a first low impedance condition and a second high impedance condition to thereby selectively couple each of said circuits to selected conductive paths or decouple each of said circuits from said conductive paths. In a specific embodiment of the invention a massive monolithic integrated circuit is configured using intercoupling means in combination with small scale random access memory semiconductor circuits. A static MOS random access memory having a 2,048 word capacity, with 9 bits/word and an 11 bit address is provided.

Abstract: A bipolar memory cell of reduced size requires only four I.sup.2 L operated transistors and three access lines. Two current injection transistors supply operating current to two inversely operated flip-flop transistors and also function as load devices as well as coupling devices. The three access lines conduct power to the cells as well as the signals for the write and read operations. A write operation is performed by ratioing the currents supplied to a memory cell array such that only a selected cell is written.

Abstract: A binary to multistate line driver and remote receiver includes a line driver comprising first and second injection logic encoder circuits. The circuits have current injectors and are connected to receive respective first and second binary signals to provide analog outputs at a signal output terminal in response to the input signals. The encoder circuits each have current injectors with substantially similar structural characteristics. The line driver further includes a reference channel circuit connected to a reference terminal to provide a reference to the encoded signals. The reference circuit has a current injector with structural characteristics substantially similar to the encoder circuit current injectors.

Abstract: A high density semiconductor structure and method is disclosed including a semiconductor body of one conductivity having a substantially planar surface. A first region of one conductivity is formed in the body and extends to the surface. A layer of opposite conductivity is interposed between the first region and the body said layer having relatively thin and uniform walls which extend to separate the first region from the body. At least one opposite conductivity region is formed entirely within the first region and extends to the surface. An opposite conductivity region is formed in the body and overlaps a portion of the layer. Lead means are provided for contacting each of the respctive regions and the body. The collector-up injection logic structure thus formed requires little or no surface area for the injection source transistor.

Abstract: Integrated injection logic circuits and semiconductor devices employing threshold functions. Multiple-collector input transistors have their collectors connected to the bases of one or more output transistors. The output transistors have different weighted levels of injection current. The switching states of the output transistors are functions of the number of and conduction state of input transistors to which the output transistor are connected and to the weight of the injection current associated with the output transistor.

Abstract: A ramp generator for driving a bar graph display which utilizes a feedback circuit to set its maximum level of the ramp.

Abstract: Unidirectional and bidirectional bipolar logic transmission gates have an input, an output, a gate control, supply and common terminals. The unilateral transmission gate circuit includes first and second switching transistors and associated first and second source tranisistors. The transistors each have collector, base and emitter electrodes, said first source transistor emitter being connected to said supply terminal. The collector of the first switching transistor is connected to the base of the second switching transistor and defines a gate logic node. The base of the first switching transistor is connected to the first input terminal and the collector of the second switching transistor is connected to the output terminal with both switching transistor emitters being connected to the common terminal.

Abstract: A multi-point probe for contacting closely spaced pads of a semiconductor device, having a flexible sheet-like member which carries the probes that make contact with the semiconductor device.

Abstract: An amplifier circuit and structure having high input impedance and having a return path for conducting amplifier DC leakage current. A common diode structure forms the return path and includes two diodes connected in series and connected in opposite conduction directions. The diode having a forward conduction direction which is in the opposite direction of the leakage current is provided with a reverse saturation current which is substantially greater than the leakage current of the amplifier. The amplifier is typically a P channel or N channel field effect transistor (FET) and the double diode structure is typically an NPN or PNP transistor.

Abstract: Solid state folded leaf spring force transducers are fabricated by batch photolithographic and etching techniques from a monocrystalline material, such as silicon. The folded leaf spring structure includes elongated gaps separating adjacent leaf spring leg portions, such elongated gaps being oriented parallel to a crystallographic axis of the monocrystalline material. In a preferred embodiment the monocrystalline material is of diamond cubic type and the leaf spring gaps extend in mutually orthogonal directions parallel to the <011> and <011> crystallographic axes, respectively. In a preferred method of fabricating the spring structure, the structure is etched from a monocrystalline wafer by means of an anisotropic etchant so as to more precisely define angles and dimensions of the resultant spring structure.

Abstract: A universal differential line driver with a single pair of outputs provides by means of a pair of control input lines selectively sourcing, sinking or high impedance conditions on the output pair.

Abstract: A method for fabricating a semiconductor diode array, utilizing an alignment tool to precisely position a plurality of diodes so that they can be bonded into a precision array. The alignment tool and a method for fabricating the tool are also disclosed.

Abstract: A collector-up binary structure of the type having spaced semiconductor regions forming a plurality of active devices for interconnection as a binary circuit is disclosed. The structure includes a semiconductor body of one conductivity having a planar surface, and spaced first, second, third and fourth transistors formed in said body. Fifth, sixth, seventh and eighth transistors are included, said fifth and sixth transistors being formed in the base regions of said second transistor and said seventh and eighth transistors being formed in the base region of said fourth transistor. Lead means provides ohmic contact to each of the respective regions of the respective transistors and interconnecting means is provided for connecting the plurality of active devices as a binary circuit. A structure further including ninth and tenth source transistors is also disclosed.

Abstract: A three-output level logic circuit in which in addition to zero and one binary logic levels a third off-logic level is provided in which the output impedance is relatively high to in effect isolate the switching circuit from a common line to which it is connected thereby allowing several switching circuits to be used in common without deleteriously affecting switching speed in an overall computer or calculator unit.